ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 165

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
16.7.2
Table 83.
I
Table 84.
SR1
2
Bit
Bit
1
0
C status register 1 (SR1)
7
EVF
RO
7
Name
Name
STOP
EVF
ITE
CR register description (continued)
SR1 register description
ADD10
Event flag
Generation of a Stop condition
Interrupt enable
RO
This bit is set by hardware as soon as an event occurs. It is cleared by software
reading SR2 register in case of error event or as described in
cleared by hardware when the interface is disabled (PE = 0).
0: No event
1: One of the following events has occurred:
This bit is set and cleared by software. It is also cleared by hardware in master
mode.
Note: This bit is not cleared when the interface is disabled (PE = 0).
In Master mode
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition
is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In Slave mode
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF = 1). In this
mode the STOP bit has to be cleared by software.
This bit is set and cleared by software and cleared by hardware when the interface
is disabled (PE = 0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (see
Figure
6
- BTF = 1 (Byte received or transmitted)
- ADSL = 1 (Address matched in Slave mode while ACK = 1)
- SB = 1 (Start condition generated in Master mode)
- AF = 1 (No acknowledge received after byte transmission)
- STOPF = 1 (Stop condition detected in Slave mode)
- ARLO = 1 (Arbitration lost in Master mode)
- BERR = 1 (Bus error, misplaced Start or Stop condition detected)
- ADD10 = 1 (Master has sent header byte)
- Address byte successfully transmitted in Master mode
68) is detected.
Figure 69
TRA
RO
5
Doc ID 13829 Rev 1
and
Table 82
BUSY
RO
4
for the relationship between the events and the
Function
Function
BTF
RO
3
ADSL
RO
2
Reset value: 0000 0000 (00h)
I2C bus interface (I2C)
Figure
M/SL
RO
1
68. It is also
165/243
RO
SB
0