ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 36

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

Supply, reset and clock management
Caution:
6.1.3
36/226
If a programming cycle is interrupted (by a RESET action), the integrity of the data in
memory will not be guaranteed.
When the Read-Out Protection is enabled through an option bit (see
bytes), these two bytes are protected against Read-out (including a re-write protection). In
Flash devices, when this protection is removed by reprogramming the option byte, these two
bytes are automatically erased.
Figure 10. RC user calibration programming cycle
Auto wakeup RC oscillator
The ST7FOX also contains an Auto wakeup RC oscillator. This RC oscillator should be
enabled to enter Auto wakeup from halt mode.
The Auto wakeup (AWU) RC oscillator can also be configured as the startup clock through
the CKSEL[1:0] option bits (see
This is recommended for applications where very low power consumption is required.
Switching from one startup clock to another can be done in run mode as follows (see
Figure
Case 1 Switching from internal RC to AWU
1.
2.
3.
4.
5.
Internal
Programming
voltage
t
PROG
Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
The RC_FLAG is cleared and the clock output is at 1.
Wait 3 AWU RC cycles till the AWU_FLAG is set
The switch to the AWU clock is made at the positive edge of the AWU clock signal
Once the switch is made, the internal RC is stopped
11):
is typically 5 ms and max 10 ms
DATA LATCHES
Byte 1 Byte 2
WRITE OF
READ OPERATION NOT POSSIBLE
ERASE CYCLE
Section 13.1: Option bytes on page
t
PROG
WRITE CYCLE
ST7FOXF1, ST7FOXK1, ST7FOXK2
READ OPERATION POSSIBLE
211).
Section 13.1: Option
RCCLAT
RCCPGM