ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 149

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

ST7FOXF1, ST7FOXK1, ST7FOXK2
10.5.5
10.5.6
6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
8. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
9. EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
10. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
11. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
Low power modes
Table 46.
Interrupts
Figure 72. Event flags and interrupt generation
Table 47.
1. The I
Mode
Wait
Halt
Arbitration Lost Event (Multimaster configuration)
subsequent EV4 is not seen.
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is
reset (RIM instruction).
*
EVF can also be set by EV6 or an error from the SR2 register.
10-bit Address Sent Event (Master mode)
Start Bit Generation Event (Master mode)
STOPF
ADD10
BERR
ARLO
ADSL
2
Address Matched Event (Slave mode)
*
C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
BTF
Stop Detection Event (Slave mode)
SB
AF
In Halt mode, the I
I
2
C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Acknowledge Failure Event
Effect of low power modes on the I
Description of interrupt events
End of byte Transfer Event
Interrupt Event
Bus Error Event
I
2
2
C interrupts cause the device to exit from Wait mode.
C interface is inactive and does not acknowledge data on the bus. The
(1)
No effect on I
ITE
I
2
Halt mode” capability.
C registers are frozen.
Description
2
2
C interface
C interface.
ADD10
STOPF
BERR
Event
ARLO
ADSL
Flag
BTF
SB
AF
Control
Enable
ITE
Bit
INTERRUPT
EVF
On-chip peripherals
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
from
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Exit
Halt
No
No
No
No
No
No
No
No