ST92F150JDV1 STMicroelectronics, ST92F150JDV1 Datasheet - Page 136

• Manufacturer Part Number: ST92F150JDV1
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST92F150JDV1

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
PLL CONFIGURATION REGISTER (PLLCONF)
R246 - Read/Write
Register Page: 55
Reset Value: 0x00 x111
Bit 7 = FREEN: PLL Free Running Mode Enable
0: PLL Free Running Mode disabled
1: PLL Free Running Mode enabled
When this bit is set, even if the DX[2:0] bits are all
set to 1, the PLL is not stopped but provides a slow
frequency back-up clock, selectable by the
CSU_CKSEL bit of the CLK_FLAG register (with-
out needing to have the LOCK bit equal to ‘1’).
Bits 5:4 = MX[1:0]: PLL Multiplication Factor.
Refer to
WARNING: After these bits are modified, take
care that the PLL lock-in time has elapsed before
setting the CSU_CKSEL bit in the CLK_FLAG reg-
ister.
Bits 2:0 = DX[2:0]: PLL output clock divider factor.
Refer to
136/429
9
FREEN
7
Table 29
Table 30
0
MX1
for multiplier settings.
for divider settings.
MX0
0
DX2
DX1
DX0
0
Table 29. PLL Multiplication Factors
Table 30. PLL Divider Factors
DX2
0
0
0
0
1
1
1
1
MX1
1
0
1
0
DX1
0
0
1
1
0
0
1
1
MX0
0
0
1
1
DX0
0
1
0
1
0
1
0
1
(PLL OFF, Reset State)
PLL CLOCK/1
PLL CLOCK/2
PLL CLOCK/3
PLL CLOCK/4
PLL CLOCK/5
PLL CLOCK/6
PLL CLOCK/7
CLOCK2 x
CLOCK2
CK
14
10
8
6