ST92F150JDV1 STMicroelectronics, ST92F150JDV1 Datasheet - Page 131

• Manufacturer Part Number: ST92F150JDV1
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST92F150JDV1

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

CLOCK MANAGEMENT (Cont’d)
7.3.6 Interrupt Generation
System clock selection modifies the CLKCTL and
CLK_FLAG registers.
The clock control unit generates an external inter-
rupt request (INTD0) in the following conditions:
– when CK_AF and CLOCK2/16 are selected or
Table 27. Summary of Operating Modes using main Crystal Controlled Oscillator
PLL x BY 14
PLL x BY 10
LOW POW-
LOW POW-
PLL x BY 8
PLL x BY 6
EXAMPLE
XTAL=4.4
ER WFI 1
ER WFI 2
deselected as system clock source,
SLOW 1
SLOW 2
SLOW3
RESET
MODE
MHz
WFI
= 11MHz
XTAL/32
XTAL/32
INTCLK
2.2*10/2
x (14/D)
x (10/D)
XTAL/2
XTAL/2
XTAL/2
XTAL/2
XTAL/2
XTAL/2
CK_AF
CK_AF
x (8/D)
x (6/D)
If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CPUCLK DIV2 PRS0-2 CSU_CKSEL MX0-1 DX2-0 LPOWFI
CK_AF/N
INTCLK/
INTCLK/
INTCLK/
INTCLK/
INTCLK/
INTCLK/
INTCLK
11MHz
STOP
STOP
N
N
N
N
N
N
X
1
1
1
1
1
1
1
1
1
1
N-1
N-1
N-1
N-1
N-1
N-1
N-1
X
X
0
0
X
X
X
X
X
1
1
1
1
0
1
– when the system clock restarts after a hardware
– when the PLL loses the programmed frequency
This interrupt can be masked by resetting the
INT_SEL bit in the CLKCTL register. Note that this
is the only case in the ST9 where an interrupt is
generated with a high to low transition.
stop (when the STOP MODE feature is availa-
ble on the specific device).
in which it was locked, and when it re-locks
1 0
0 0
1 1
0 1
00
00
X
X
X
X
X
111
111
001
D-1
D-1
D-1
D-1
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
WFI_CK
SEL
X
X
X
X
X
X
X
0
1
0
XT_DIV16
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X
X
X
1
1
1
1
1
0
1
1
9