ST72321AR7 STMicroelectronics, ST72321AR7 Datasheet - Page 26

• Manufacturer Part Number: ST72321AR7
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321AR7

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72321Rx ST72321ARx ST72321Jx
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
■
■
■
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 13. Reset Block Diagram
26/193
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by
option byte)
RESET vector fetch
RESET
section 14.1 on page
Figure
12:
V
Figure
175).
DD
R
ON
13:
Filter
Figure 12. RESET Sequence Phases
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed.
For this reason, it is recommended to keep the
RESET pin in low state until programming mode is
entered, in order to avoid unwanted behavior.
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
“CONTROL
page 159
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized (see
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
GENERATOR
PULSE
Active Phase
for more details.
PIN
256 or 4096 CLOCK CYCLES
INTERNAL RESET
RESET
CHARACTERISTICS”
ON
weak pull-up resistor.
WATCHDOG RESET
LVD RESET
Figure
INTERNAL
RESET
14). This de-
VECTOR
h(RSTL)in
FETCH
on
in