ST72321AR7 STMicroelectronics, ST72321AR7 Datasheet - Page 115

• Manufacturer Part Number: ST72321AR7
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321AR7

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

10.7 I
10.7.1 Introduction
The I
tween the microcontroller and the serial I
provides both multimaster and slave functions,
and controls all I
tocol, arbitration and timing. It supports fast I
mode (400kHz).
10.7.2 Main Features
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I
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I
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10.7.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
Figure 64. I
2
2
C Master Features:
C Slave Features:
Parallel-bus/I
Multi-master capability
7-bit/10-bit Addressing
SMBus V1.1 Compliant
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
Clock generation
I
Arbitration Lost Flag
End of byte transmission flag
Transmitter/Receiver Flag
Start bit detection flag
Start and Stop generation
Stop bit detection
I
Detection of misplaced start or stop condition
Programmable I
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
2
2
C bus busy flag
C bus busy flag
2
2
C Bus Interface serves as an interface be-
C BUS INTERFACE (I2C)
2
SCL
SDA
C BUS Protocol
2
CONDITION
C protocol converter
2
C bus-specific sequencing, pro-
2
START
C Address detection
MSB
1
2
C bus. It
2
2
C
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I
and a Fast I
ware.
Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to
ure
64.
ST72321Rx ST72321ARx ST72321Jx
8
2
C bus. This selection is made by soft-
ACK
9
CONDITION
STOP
VR02119B
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2
C bus
Fig-
2
C