ST72321M9 STMicroelectronics, ST72321M9 Datasheet - Page 151

• Manufacturer Part Number: ST72321M9
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72321M9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72321M6 ST72321M9
11.8 I/O PORT PIN CHARACTERISTICS
11.8.1 General Characteristics
Subject to general operating conditions for V
Figure 76. Unused I/O Pins configured as input
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V
tion. A positive injection is induced by V
on page 135
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see
based on design simulation and/or technology characteristics, not tested in production.
5. The R
scribed in
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
151/175
ΣI
I
Symbol
INJ(PIN)
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
t
t
INJ(PIN)
t
r(IO)out
f(IO)out
w(IT)in
V
V
R
C
V
V
V
V
I
I
hys
hys
PU
S
IH
IH
L
IO
IL
IL
3)
PU
3)
Figure
pull-up equivalent resistor is based on a resistive transistor (corresponding I
for more details.
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Injected Current on PC6
Injected Current on an I/O pin
Total injected current (sum of all I/O
and control pins)
Input leakage current
Static current consumption
Weak pull-up equivalent resistor
I/O pin capacitance
Output high to low level fall time
Output low to high level rise time
External interrupt pulse time
77).
V
DD
Parameter
10kΩ
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
1)
1)
1)
1)
IN
>V
ST7XXX
6)
ST7XXX
DD
1)
5)
1)
2)
2)
while a negative injection is induced by V
CMOS ports
TTL ports
V
V
Floating input mode
V
C
Between 10% and 90%
IN
DD
DD
SS
IN
L
=50 pF
maximum must be respected, otherwise refer to I
, f
=
≤
=5 V
V
V
OSC
SS
IN
Conditions
≤
V
, and T
DD
Figure 77. Typical I
V
DD
=5 V
A
4)
unless otherwise specified.
90
80
70
60
50
40
30
20
10
0
2
2.5
0.7xV
Min
50
2
0
1
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
3
DD
PU
3.5
IN
vs. V
PU
<V
V dd(V)
Typ
400
120
0.7
25
25
4
current characteristics de-
1
5
SS
DD
. Refer to
4.5
with V
0.3xV
5
INJ(PIN)
Max
± 25
250
Figure
0.8
± 4
+4
±1
5.5
section 11.2.2
IN
DD
=V
specifica-
6
76). Data
SS
Unit
t
mA
CPU
μA
kΩ
pF
ns
V