ST72561AR7 STMicroelectronics, ST72561AR7 Datasheet - Page 94

• Manufacturer Part Number: ST72561AR7
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72561AR7

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72561
8-BIT TIMER (Cont’d)
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFh to 00h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CTR register.
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– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
Notes: The TOF bit is not cleared by accesses to
ACTR register. The advantage of accessing the
ACTR register rather than the CTR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).