STM8L101F3 STMicroelectronics, STM8L101F3 Datasheet - Page 29
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
STM8L101F3
Manufacturer Part Number
STM8L101F3
Description
Ultra Low Power MCUs, STM8L
Manufacturer
STMicroelectronics
Datasheet
1.STM8L101G2.pdf
(81 pages)
Specifications of STM8L101F3
Low Power Consumption (halt
0.3 μA, Active-halt
Temp. Range
-40 to 85 °C and 125 °C
Three Low Power Modes
Wait, Active-halt, Halt
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM8L101F3P3
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM8L101F3P6
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM8L101F3P6B
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM8L101F3P6TR
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM8L101F3U6
Manufacturer:
ST
Quantity:
20 000
STM8L101xx
Table 7.
0x00 52DF
0x00 528A
0x00 528B
0x00 528C
0x00 528D
0x00 528E
0x00 52E0
0x00 52E1
0x00 52E2
0x00 52E3
0x00 52E4
0x00 52E5
0x00 52E6
0x00 52E7
0x00 52E8
0x00 5280
0x00 5281
0x00 5282
0x00 5283
0x00 5284
0x00 5285
0x00 5286
0x00 5287
0x00 5288
0x00 5289
0x00 528F
0x00 5290
0x00 5291
0x00 5292
0x00 5293
0x00 5294
0x00 5295
0x00 5296
Address
to
General hardware register map (continued)
Block
TIM3
TIM4
Register label
TIM3_CCMR1
TIM3_CCMR2
TIM3_CNTRH
TIM3_CCR1H
TIM3_CCR2H
TIM3_CCER1
TIM3_CNTRL
TIM3_CCR1L
TIM3_CCR2L
TIM3_SMCR
TIM4_SMCR
TIM3_ARRH
TIM3_PSCR
TIM4_CNTR
TIM4_PSCR
TIM3_ARRL
TIM3_OISR
TIM3_EGR
TIM4_EGR
TIM4_ARR
TIM3_BKR
TIM3_CR1
TIM3_CR2
TIM3_ETR
TIM3_SR1
TIM3_SR2
TIM4_CR1
TIM4_CR2
TIM4_SR1
TIM3_IER
TIM4_IER
Doc ID 15275 Rev 11
Reserved area (74 bytes)
TIM3 capture/compare enable register 1
TIM3 capture/compare mode register 1
TIM3 capture/compare mode register 2
TIM3 capture/compare register 1 high
TIM3 capture/compare register 2 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 low
TIM4 Slave mode control register
TIM3 slave mode control register
TIM3 event generation register
TIM4 event generation register
TIM3 auto-reload register high
TIM3 output idle state register
TIM3 interrupt enable register
TIM4 interrupt enable register
TIM3 auto-reload register low
TIM4 auto-reload register low
TIM3 external trigger register
TIM3 prescaler register
TIM4 prescaler register
TIM3 control register 1
TIM3 control register 2
TIM4 control register 1
TIM4 control register 2
TIM4 Status register 1
TIM3 status register 1
TIM3 status register 2
TIM3 break register
TIM3 counter high
TIM3 counter low
Register name
TIM4 counter
Memory and register map
status
Reset
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
29/81