BUK9675-55A NXP Semiconductors, BUK9675-55A Datasheet

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

BUK9675-55A

Manufacturer Part Number
BUK9675-55A
Description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet

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1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
Table 1.
Symbol
V
I
P
D
DS
tot
BUK9675-55A
N-channel TrenchMOS logic level FET
Rev. 2 — 8 February 2011
AEC Q101 compliant
Low conduction losses due to low
on-state resistance
12 V and 24 V loads
Automotive and general purpose
power switching
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
Conditions
T
V
see
T
j
mb
GS
≥ 25 °C; T
Figure
= 25 °C; see
= 5 V; T
1; see
mb
j
≤ 175 °C
= 25 °C;
Figure 2
Figure 3
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
Motors, lamps and solenoids
Min
-
-
-
Product data sheet
Typ
-
-
-
Max Unit
55
20
62
V
A
W

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BUK9675-55A Summary of contents

Page 1

... BUK9675-55A N-channel TrenchMOS logic level FET Rev. 2 — 8 February 2011 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. ...

Page 2

... Simplified outline SOT404 (D2PAK) Description plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET Min = Figure 12 ...

Page 3

... P der (%) 150 200 T (°C) mb Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET Min - - -10 Figure 1; - Figure 1 - ≤ 10 µ -55 -55 - ° ...

Page 4

... Conditions see Figure 4 mounted on printed-circuit board; minimum footprint −5 −4 − All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET 03nd46 = 10 μ 100 μ 100 (V) DS ...

Page 5

... see Figure /dt = -100 A/µ - ° All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET Min Typ Max 0 1 2.3 - ...

Page 6

... V (V) DS Fig 6. 03aa36 max (V) GS Fig 8. All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET 120 DSon 100 Drain-source on-state resistance as a function of gate-source voltage; typical values 15 g ...

Page 7

... V (V) GS Fig 10. Gate-source voltage as a function of turn-on 03aa33 120 180 ( ° Fig 12. Drain-source on-state resistance as a function All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET ( 44( 14( ...

Page 8

... Fig 14. Input, output and reverse transfer capacitances ( 175 ° 0.5 1.0 All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET C iss C oss C rss 0 −2 − function of drain-source voltage; typical values 03nd38 = 25 ° ...

Page 9

... max. 1.60 10.30 2.90 15.80 11 2.54 1.20 9.70 2.10 14.80 REFERENCES JEDEC JEITA All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET mounting base 2.60 2.20 EUROPEAN ISSUE DATE PROJECTION 05-02-11 06-03-16 © NXP B.V. 2011. All rights reserved. SOT404 ...

Page 10

... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Type number BUK9675-55A separated from data sheet BUK9575_9675_55A v.1. Product specification All information provided in this document is subject to legal disclaimers. ...

Page 11

... In case an individual All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET © NXP B.V. 2011. All rights reserved ...

Page 12

... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 2 — 8 February 2011 BUK9675-55A N-channel TrenchMOS logic level FET Trademarks © NXP B.V. 2011. All rights reserved ...

Page 13

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 8 February 2011 Document identifier: BUK9675-55A ...

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