LPC2290 NXP Semiconductors, LPC2290 Datasheet - Page 33

The LPC2290 microcontroller is based on a 16/32-bit ARM7TDMI-S CPU with real-timeemulation and embedded trace support

LPC2290

Manufacturer Part Number
LPC2290
Description
The LPC2290 microcontroller is based on a 16/32-bit ARM7TDMI-S CPU with real-timeemulation and embedded trace support
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
Table 9.
C
[1]
[2]
[3]
[4]
[5]
Table 10.
LPC2290_3
Product data sheet
Symbol
t
t
t
t
t
t
t
Access cycle
standard read
standard write
burst read - initial
burst read - subsequent 3
BLSHDNV
CHDV
CHWEL
CHBLSL
CHWEH
CHBLSH
CHDNV
L
= 25 pF, T
Except on initial access, in which case the address is set up T
T
Latest of address valid, CS LOW, OE LOW to data valid.
Address valid to data valid.
Earliest of CS HIGH, OE HIGH, address change to data invalid.
cy(CCLK)
External memory interface dynamic characteristics
Parameter
BLS HIGH to data invalid
time
XCLK HIGH to data valid
time
XCLK HIGH to WE LOW
time
XCLK HIGH to BLS LOW
time
XCLK HIGH to WE HIGH
time
XCLK HIGH to BLS HIGH
time
XCLK HIGH to data invalid
time
Standard read access specifications
=
amb
1
CCLK.
= 40 C
Max frequency
f
f
f
f
MAX
MAX
MAX
MAX
--------------------------------
t
--------------------------------- -
t
------------------------------- -
t
-------------------------------- -
t
RAM
WRITE
INIT
ROM
2
2
1
Conditions
+
+
+
WST 1
WST 1
+
+
WST 2
+
1
20 ns
20 ns
+
20 ns
Rev. 03 — 16 November 2006
5 ns
16/32-bit ARM microcontroller with external memory interface
WST 1
WST setting
WST
integer
N/A
WST 1
WST 2
cy(CCLK)
[2]
0; round up to
Min
(2
-
-
-
-
-
-
t
------------------------------- - 2
t
-------------------------------- 2
t
------------------------------------------- -
INIT
RAM
WRITE
t
t
cy CCLK
earlier.
cy CCLK
…continued
T
t
cy CCLK
+
cy(CCLK)
+
20 ns
20 ns
t
CYC
)
+
5
5
Memory access time requirement
t
t
t
t
INIT
RAM
WRITE
ROM
t
t
t
cy CCLK
cy CCLK
cy CCLK
Typ Max
-
-
-
-
-
-
-
t
cy CCLK
(2
10
10
10
10
10
10
LPC2290
T
20 ns
© NXP B.V. 2006. All rights reserved.
2
2
cy(CCLK)
+
+
1
WST 1
WST 1
+
WST 2
) + 5 ns
20 ns
33 of 41
20 ns
Unit
ns
ns
ns
ns
ns
ns
5 ns

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