LPC2290 NXP Semiconductors, LPC2290 Datasheet - Page 19

• Manufacturer Part Number: LPC2290
• Description: The LPC2290 microcontroller is based on a 16/32-bit ARM7TDMI-S CPU with real-timeemulation and embedded trace support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2290_3
Product data sheet
6.10.2 UART features available in LPC2290/01 only
6.11.1 Features
6.11 I
6.12 SPI serial I/O controller
The I
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
The LPC2290 contains two SPIs. The SPI is a full duplex serial interface, designed to be
able to handle multiple masters and slaves connected to a given bus. Only a single master
and a single slave can communicate on the interface during a given data transfer. During a
data transfer the master always sends a byte of data to the slave, and the slave always
sends a byte of data to the master.
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C-bus serial I/O controller
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in baud rate generator.
Standard modem interface signals included on UART1.
The transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs and hardware (CTS/RTS) flow control on UART1 only.
Fractional baud rate generator enables standard baud rates such as 115200 to be
achieved with any crystal frequency above 2 MHz.
Auto-bauding.
Auto-CTS/RTS flow-control fully implemented in hardware.
Compliant with standard I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
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C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
C-bus implemented in LPC2290 supports bit rate up to 400 kbit/s (Fast I
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C-bus may be used for test and diagnostic purposes.
Rev. 03 — 16 November 2006
16/32-bit ARM microcontroller with external memory interface
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C-bus interface.
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C-bus is a multi-master bus, it can be
LPC2290
© NXP B.V. 2006. All rights reserved.
2
C-bus).
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