LPC1820FET100 NXP Semiconductors, LPC1820FET100 Datasheet - Page 109

• Manufacturer Part Number: LPC1820FET100
• Description: The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 16.
T
[1]
[2]
LPC1850_30_20_10
Preliminary data sheet
Symbol
T
SSP master
t
t
t
t
SSP slave
T
T
t
t
t
t
amb
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
cy(clk)
cy(PCLK)
cy(clk)
T
main clock frequency f
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
T
= 25
cy(clk)
cy(clk)

= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
= 12  T
C; 2.2 V
Parameter
clock cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time
PCLK cycle time
clock cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time
Dynamic characteristics: SSP pins in SPI mode
11.8 SSP interface
cy(PCLK)

V
DD(REG)(3V3)
main
.
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
Conditions
full-duplex mode
when only
transmitting
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode

3.6 V; 2.7 V
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 15 December 2011

main
V
DD(IO)
. The clock cycle time derived from the SPI bit rate T
[1]
[2]

Min
-
-
-
-
-
-
10
120
-
-
-
-
3.6 V. Simulated values.
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
Typ
40
20
8.8
5.0
3.9
0.4
-
10.5
1
4.0
0.2
Max
-
-
-
-
-
-
-
-
-
-
-
cy(clk)
© NXP B.V. 2011. All rights reserved.
is a function of the
109 of 157
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns