LPC1820FET100 NXP Semiconductors, LPC1820FET100 Datasheet - Page 106

• Manufacturer Part Number: LPC1820FET100
• Description: The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 13.
T
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
LPC1850_30_20_10
Preliminary data sheet
Symbol
t
t
t
HIGH
HD;DAT
SU;DAT
amb
Fig 24. I
Parameters are valid over operating temperature range unless otherwise specified.
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
bridge the undefined region of the falling edge of SCL.
C
The maximum t
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
The maximum t
t
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
A Fast-mode I
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
Standard-mode I
VD;ACK
=
b
SDA

= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
SCL
40
2
by a transition time. This maximum must only be met if the device does not stretch the LOW period (t

Dynamic characteristic: I
C-bus pins clock timing
C to +85
70 %
30 %
S
2
Parameter
HIGH period of the SCL clock
data hold time
data set-up time
t
C-bus device can be used in a Standard-mode I
f
f
HD;DAT
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

C; 2.2 V
t
f
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t
70 %
30 %
1 / f

SCL
V
DD(REG)(3V3)
t
HD;DAT
2
70 %
30 %
C-bus pins
70 %
30 %
All information provided in this document is subject to legal disclaimers.
f
.
t
SU;DAT

Rev. 3.1 — 15 December 2011
3.6 V.
[2][3][7]
[8][9]
[1]
70 %
30 %
2
C-bus system but the requirement t
Conditions
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
t
LOW
r(max)
t
HIGH
+ t
32-bit ARM Cortex-M3 microcontroller
70 %
30 %
SU;DAT
LPC1850/30/20/10
Min
4.0
0.6
0.26
0
0
0
250
100
50
t
VD;DAT
= 1000 + 250 = 1250 ns (according to the
SU;DAT
IH
(min) of the SCL signal) to
= 250 ns must then be met.
LOW
© NXP B.V. 2011. All rights reserved.
) of the SCL signal. If
Max
-
-
-
-
-
-
-
-
-
002aaf425
f
is specified at
106 of 157
VD;DAT
Unit
s
s
s
s
s
s
ns
ns
ns
or