ADP1875 Analog Devices, ADP1875 Datasheet - Page 7

• Manufacturer Part Number: ADP1875
• Description: Synchronous Buck Controller with Constant On-Time, Valley Current Mode, and Power Saving Mode
• Manufacturer: Analog Devices

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
VIN
COMP
EN
FB
GND
RES
VREG
VREG_IN
TRACK
SS
PGOOD
DRVL
PGND
DRVH
SW
BST
Description
High-Side Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
Output of the Error Amplifier. Connect the compensation network between this pin and AGND to achieve stability
(see the Compensation Network section).
Connect to VREG to Enable IC. When pulled down to AGND externally, disables the IC.
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane
(see the Layout Considerations section).
Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).
Internal Regulator Supply Bias Voltage for the ADP1874/ADP1875 Controller (Includes the Output Gate Drivers). A
bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VREG and GND are recommended.
Input to the Internal LDO. Tie this pin directly to Pin 7 (VREG).
Tracking Input. If the tracking function is not used, it is recommended to connect TRACK to VREG through a resistor
higher than 1 MΩ or simply connect TRACK between 0.7 V and 2 V to reduce the bias current going into the pin.
Soft Start Input. Connect an external capacitor to GND to program the soft start period. Capacitance value of 10 nF for
every 1 ms of soft start delay.
Open-Drain Power Good Output. Sinks current when FB is out of regulation or during thermal shutdown. Connect a
3 kΩ resistor between PGOOD and VREG. Leave unconnected if not used.
Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting
pin (see Figure 69).
Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET.
Drive Output for the External Upper-Side, N-Channel MOSFET.
Switch Node Connection.
Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between
VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between
VREG and BST for increased gate drive capability.
VREG_IN
COMP
VREG
GND
RES
VIN
EN
FB
Figure 3. Pin Configuration
1
2
3
4
5
6
7
8
Rev. 0 | Page 7 of 44
(Not to Scale)
ADP1874/
ADP1875
TOP VIEW
16
15
14
13
12
11
10
9
BST
SW
DRVH
PGND
DRVL
PGOOD
SS
TRACK
ADP1874/ADP1875