ADP1875 Analog Devices, ADP1875 Datasheet - Page 30

• Manufacturer Part Number: ADP1875
• Description: Synchronous Buck Controller with Constant On-Time, Valley Current Mode, and Power Saving Mode
• Manufacturer: Analog Devices

ADP1874/ADP1875
Diode Conduction Loss
The ADP1874/ADP1875 employ anti cross-conduction circuitry
that prevents the upper- and lower-side MOSFETs from conducting
current simultaneously. This overlap control is beneficial, avoiding
large current flow that may lead to irreparable damage to the
external components of the power stage. However, this blanking
period comes with the trade-off of a diode conduction loss
occurring immediately after the MOSFET change states and
continuing well into idle mode. The amount of loss through the
body diode of the lower-side MOSFET during the anti-overlap
state is given by the following expression:
where:
t
time periods).
t
V
(See the selected external MOSFET data sheet for more
information about the V
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1874/ADP1875
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).
BODY(LOSS)
SW
F
is the forward drop of the body diode during conduction.
Figure 88. Body Diode Conduction Time vs. Low Voltage Input (VREG)
is the period per switching cycle.
P
P
DCR
BODY
80
72
64
56
48
40
32
24
16
8
2.7
is the body conduction time (see Figure 88 for dead
(
LOSS
(
LOSS
)
)
=
=
DCR
t
BODY
3.4
t
×
SW
I
(
LOSS
2
LOAD
F
1MHz
300kHz
parameter.)
)
×
+ Core Loss
I
VREG (V)
LOAD
4.1
×
V
F
×
2
4.8
+125°C
+25°C
–40°C
5.5
Rev. 0 | Page 30 of 44
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
switching frequencies.
If bulk electrolytic capacitors are used, it is recommended to use
multilayered ceramic capacitors (MLCC) in parallel due to their
low ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across the
drain of the upper-side MOSFET and the source terminal of the
lower-side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper-side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at Time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
where:
V
I
ESR is the equivalent series resistance rating of the input capacitor.
Inserting V
calculate the minimum input capacitor requirement gives
or
where D = 50%.
LOAD,MAX
RIPP
V
I
is usually 1% of the minimum voltage input.
C
C
CIN
MAX,RIPPLE
IN,min
IN,min
is the maximum load current.
,
RMS
MAX,RIPPLE
=
=
=
V
4
I
= V
I
LOAD
MAX
LOAD
f
SW
I
RIPP
LOAD
V
,
,
into the charge balance equation to
RIPPLE
MAX
,
MAX
MAX
+ (I
,
MAX
×
,
RIPPLE
LOAD,MAX
×
V
D
OUT
1 (
f
SW
−
×
V
D
× ESR)
(
V
OUT
)
IN
−
V
OUT
)