ADP1875 Analog Devices, ADP1875 Datasheet - Page 29

• Manufacturer Part Number: ADP1875
• Description: Synchronous Buck Controller with Constant On-Time, Valley Current Mode, and Power Saving Mode
• Manufacturer: Analog Devices

EFFICIENCY CONSIDERATION
One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
•
•
•
•
•
The following are the losses experienced through the external
component during normal switching operation:
•
•
•
•
•
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper-side MOSFET is directly pro-
portional to the duty-cycle (D) for each switching period, and
the power loss through the lower-side MOSFET is directly
proportional to 1 − D for each switching period. The selection
of MOSFETs is governed by the maximum dc load current that
the converter is expected to deliver. In particular, the selection
of the lower-side MOSFET is dictated by the maximum load
current because a typical high current application employs duty
cycles of less than 50%. Therefore, the lower-side MOSFET is
in the on state for most of the switching period.
V
and the source that starts channel conduction.
R
conduction.
Q
C
C
Channel conduction loss (both the MOSFETs)
MOSFET driver loss
MOSFET switching loss
Body diode conduction loss (lower-side MOSFET)
Inductor loss (copper and core loss)
P
DS (ON)
GS (TH)
N1
N2
N1,N2(CL)
G
is the total gate charge.
is the input capacitance of the upper-side switch.
is the input capacitance of the lower-side switch.
is the MOSFET voltage applied between the gate
is the MOSFET on resistance during channel
=
[
D
×
R
N1(ON)
+
(
1
−
D
)
×
R
N2(ON)
]
×
I
LOAD
2
Rev. 0 | Page 29 of 44
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The con-
tributing factors are the dc current flowing through a driver
during operation and the Q
where:
C
C
I
V
(VREG) minus the rectifier drop (see Figure 87)).
VREG is the bias voltage.
Switching Loss
The SW node transitions due to the switching activities of the
upper- and lower-side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times.
This can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions:
where:
C
R
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
or
BIAS
upperFET
lowerFET
TOTAL
GATE
DR
is the dc current flowing into the upper- and lower-side drivers.
is the driver bias voltage (that is, the low input voltage
Figure 87. Internal Rectifier Voltage Drop vs. Switching Frequency
t
P
[
P
P
VREG
SW-TRANS
is the gate input resistance of the external MOSFET.
800
720
640
560
480
400
320
240
160
SW(LOSS)
SW
DR
is the C
80
is the input gate capacitance of the lower-side MOSFET.
is the input gate capacitance of the upper-side MOSFET.
300
(
(
LOSS
LOSS
×
= R
)
)
= f
(
GD
=
=
400
f
SW
SW
[
VREG = 2.7V
VREG = 3.6V
VREG = 5.5V
GATE
t
V
+ C
SW
× R
DR
C
t
-
SW
lowerFET
TRANS
GS
× C
SWITCHING FREQUENCY (kHz)
×
500
GATE
(
of the external MOSFET.
f
TOTAL
SW
GATE
×
× C
V
C
I
REG
600
LOAD
upperFET
TOTAL
parameter of the external MOSFETs.
+
×
I
ADP1874/ADP1875
× I
700
V
BIAS
V
IN
DR
LOAD
)
×
]
+
2
800
× V
I
BIAS
IN
)
]
× 2
+
900
+125°C
+25°C
–40°C
1000