ADUC816 Analog Devices, ADUC816 Datasheet - Page 54

• Manufacturer Part Number: ADUC816
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC816

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

TIMER/COUNTER 0 AND 1 OPERATING MODES
The following paragraphs describe the operating modes for timer/
counters 0 and 1. Unless otherwise noted, it should be assumed
that these modes of operation are the same for timer 0 as for timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter with a divide-by-32
prescaler. Figure 33 shows mode 0 operation.
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer overflow
flag TF0. The overflow flag, TF0, can then be used to request an
interrupt. The counted input is enabled to the timer when TR0 = 1
and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer
to be controlled by external input INT0, to facilitate pulsewidth
measurements. TR0 is a control bit in the special function regis-
ter TCON; Gate is in TMOD. The 13-bit register consists of all
eight bits of TH0 and the lower five bits of TL0. The upper three
bits of TL0 are indeterminate and should be ignored. Setting the
run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. Mode 1 is shown in Figure 34.
P3.4/T0
P3.2/INT0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
P3.4/T0
P3.2/INT0
CORE
CLK*
CORE
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
CLK*
GATE
GATE
12
12
TR0
TR0
C/T = 0
C/T = 1
C/T = 0
C/T = 1
CONTROL
CONTROL
(8 BITS)
(5 BITS)
TL0
TL0
(8 BITS)
(8 BITS)
TH0
TF0
TH0
TF0
INTERRUPT
INTERRUPT
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 35. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which is preset by software. The reload leaves TH0 unchanged.
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 36. TL0
uses the timer 0 control bits: C/T, Gate, TR0, INT0, and TF0.
TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from timer 1. Thus, TH0
now controls the “timer 1” interrupt. Mode 3 is provided for
applications requiring an extra 8-bit timer or counter.
When timer 0 is in Mode 3, timer 1 can be turned on and off by
switching it out of, and into, its own Mode 3, or can still be used by
the serial interface as a
in any application not requiring an interrupt from timer 1 itself.
P3.2/INT0
P3.2/INT0
CORE
P3.4/T0
CLK*
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
P3.4/T0
CLK/12
CORE
GATE
GATE
CORE
CLK*
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
TR1
12
12
TR0
TR0
C/T = 0
C/T = 1
C/T = 0
C/T = 1
CORE
CLK/12
CONTROL
CONTROL
CONTROL
RELOAD
(8 BITS)
(8 BITS)
. In fact, it can be used,
(8 BITS)
(8 BITS)
TH0
TL0
TH0
TL0
TF0
TF1
INTERRUPT
TF0
INTERRUPT
INTERRUPT
REV. A