ADUC816 Analog Devices, ADUC816 Datasheet - Page 42

• Manufacturer Part Number: ADUC816
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC816

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

On-Chip PLL
The ADuC816 is intended for use with a 32.768 kHz watch crys-
tal. A PLL locks onto a multiple (384) of this to provide a stable
12.582912 MHz clock for the system. The core can operate at
this frequency or at binary submultiples of it to allow power
saving in cases where maximum core performance is not
PLLCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
O
S
C
_
P
D
Name
OSC_PD
LOCK
---
LTEA
FINT
CD2
CD1
CD0
L
O
C
K
PLL Control Register
D7H
03H
No
Description
Oscillator Power-Down Bit.
This feature allows the TIC to continue counting even in power-down mode.
PLL Lock Bit.
This is a read only bit.
external crystal becomes subsequently disconnected the PLL will rail and the core will halt.
This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode,
the PLL output can be 12.58 MHz ± 20%.
Reserved for future use; should be written with “0.”
Reading this bit returns the state of the external EA pin latched at reset or power-on.
Fast Interrupt Response Bit.
regardless of the configuration of the CD2–0 bits (see below). Once user code has returned from an
interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits.
CPU (Core Clock) Divider Bits.
This number determines the frequency at which the microcontroller core will operate.
CD2
0
0
0
0
1
1
1
1
-
automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. If the
by user enabling the response to any interrupt to be executed at the fastest core clock frequency,
by user to halt the 32 kHz oscillator in power-down mode.
- -
by user to enable the 32 kHz oscillator in power-down mode.
automatically at power-on to indicate the PLL is not correctly tracking the crystal clock.
by user to disable the fast interrupt response feature.
Table XV. PLLCON SFR Bit Designations
CD1
0
0
1
1
0
0
1
1
L
T
E
A
CD0
0
1
0
1
0
1
0
1
required. The default core clock is the PLL clock divided by
8 or 1.572864 MHz. The ADC clocks are also derived from the
PLL clock, with the modulator rate being the same as the crystal
oscillator frequency. The above choice of frequencies ensures
that the modulators and the core will be synchronous, regardless
of the core clock rate. The PLL control register is PLLCON.
F
I
N
T
Core Clock Frequency (MHz)
12.582912
6.291456
3.145728
1.572864 (Default Core Clock Frequency)
0.786432
0.393216
0.196608
0.098304
C
D
2
C
D
1
C
D
REV. A
0