ADUC816 Analog Devices, ADUC816 Datasheet
ADUC816
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ADUC816 Summary of contents
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... I/O ports (SPI, UART, and I On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. A functional block diagram of the ADuC816 is shown above with a more detailed block diagram shown in Figure 12. ...
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... FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . 18 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 19 ADuC816 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 OVERVIEW OF MCU-RELATED SFRS . . . . . . . . . . . . . . . . . . 23 Accumulator SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 B SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Stack Pointer SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program Status Word SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power Control SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . 24 SFR INTERFACE TO THE PRIMARY AND AUXILIARY ADCs ...
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... DAC PERFORMANCE 6 DC Specifications Resolution Relative Accuracy Differential Nonlinearity Offset Error 7 Gain Error Specifications Voltage Output Settling Time Digital-to-Analog Glitch Energy REV. A ADuC816BS Unit 5.4 Hz min 105 Hz max 16 Bits min 13 Bits p-p typ 16 Bits p-p typ See Table IX and X in ADC Description ± ...
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... Input Span ANALOG (DAC) OUTPUTS Voltage Range Resistive Load Capacitive Load Output Impedance I SINK TEMPERATURE SENSOR Accuracy Thermal Impedance (θ ADuC816BS Unit 1.25 ± min/max 45 dBs typ 100 ppm/°C typ 2.5 ± min/max 50 dBs typ ± 100 ppm/°C typ ± ...
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... P1.0, P1.1, Ports 2 and 3 Input Capacitance CRYSTAL OSCILLATOR (XTAL1 AND XTAL2) Logic Inputs, XTAL1 Only V , Input Low Voltage INL V , Input High Voltage INH XTAL1 Input Capacitance XTAL2 Output Capacitance REV. A ADuC816BS Unit –100 nA typ +100 nA typ ± typ 0.03 %/°C typ μA typ –200 ± 10 ...
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... After WDT Reset in Normal Mode FLASH/EE MEMORY RELIABILITY CHARACTERISTICS 14 Endurance 15 Data Retention POWER REQUIREMENTS Power Supply Voltage Nominal Operation Nominal Operation Nominal Operation Nominal Operation DV DD ADuC816BS Unit 2 2.4 V min 2.4 V min 0.4 V max 0.4 V max 0.4 V ± 10 μA max 5 pF typ 2.63 V min 4.63 V max ± ...
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... PCON Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR power supply current will typically increase operation) and operation) during a Flash/EE memory program or erase cycle. DD Specifications subject to change without notice REV. A ADuC816BS Unit Test Conditions/Comments 16 max DV 2 ...
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... C LOAD 4 ADuC816 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a Stable 12.583 MHz internal clock for the system. The core can operate at this frequency binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 1.57 MHz. ...
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Parameter EXTERNAL PROGRAM MEMORY t ALE Pulsewidth LHLL t Address Valid to ALE Low AVLL t Address Hold after ALE Low LLAX t ALE Low to Valid Instruction In LLIV ALE Low to PSEN Low t LLPL PSEN Pulsewidth t ...
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Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t RHDX ...
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Parameter EXTERNAL DATA MEMORY WRITE CYCLE WR Pulsewidth t WLWH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX ALE Low to WR Low t LLWL Address Valid to WR Low t AVWL Data Valid ...
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Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after Clock ...
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Parameter 2 I C-COMPATIBLE INTERFACE TIMING t SCLOCK Low Pulsewidth L t SCLOCK High Pulsewidth H t Start Condition Hold Time SHD t Data Setup Time DSU t Data Hold Time DHD t Setup Time for Repeated Start RSU t ...
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Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time ...
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Parameter SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data Input Setup Time before ...
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Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge ...
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Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge ...
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... Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 AGND and DGND are shorted internally on the ADuC816. 2 Applies to P1.2 to P1.7 pins operating in analog or digital input modes. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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... External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data memory. I/O External Data Memory Read Strobe. Enables the data from an external data memory to Port 0. –19– ADuC816 1 42 PIN 1 INDICATOR ADuC816 TOP VIEW (Not to Scale NOTES 1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED. 56-Lead LFCSP ...
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... I Input to the Crystal Oscillator Inverter O Output from the Crystal Oscillator Inverter. (See the ADuC816 Hardware Design Considerations section for description.) I/O External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh.When held low, this input enables the device to fetch all instructions from external program memory ...
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... REV. A Figure 12. 52-MQFP Block Diagram –21– ADuC816 ...
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... MEMORY ORGANIZATION As with all 8051-compatible devices, the ADuC816 has sepa- rate address spaces for Program and Data memory as shown in Figure 13 and Figure 14. If the user applies power or resets the device while the EA pin is pulled low, the part will execute code from the external pro- gram space, otherwise the part defaults to code execution from its internal 8 Kbyte Flash/EE program memory ...
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... The SFR space is mapped to the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC816 via the SFR area is shown in Figure 16. A complete SFR map is shown in Figure 17. ...
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SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general- purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip ...
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... Reserved for Future Use. 0 --- Reserved for Future Use. REV. A ICON: ADC0H/M : ADC1H/L: OF0H/M : OF1H/L: GN0H/M : GN1H/L: To maintain code compatibility with the ADuC824 the low-byte SFR associated with these register groups that is omitted on the ADuC816 Table III. ADCSTAT SFR Bit Designations by hardware on completion of ADC conversion or calibration cycle ...
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ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable Bit Name Description 7 --- Reserved for Future Use. ...
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ADC0CON (Primary ADC Control Register) Used to configure the Primary ADC for range, channel selection, external Ref enable, and unipolar or bipolar coding. SFR Address D2H Power-On Default Value 07H Bit Addressable ...
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ADC1CON (Auxiliary ADC Control Register) Used to configure the Auxiliary ADC for channel selection, external Ref enable and unipolar or bipolar coding. It should be noted that the Auxiliary ADC only operates on a fixed input range of ± V ...
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ICON (Current Sources Control Register) Used to control and configure the various excitation and burnout current source options available on-chip. SFR Address D5H Power-On Default Value 00H Bit Addressable Bit Name Description ...
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OF0H/OF0M (Primary ADC Offset Calibration Registers These two 8-bit registers hold the 16-bit offset calibration coefficient for the Primary ADC. These registers are configured at power- on with a factory default value of 8000Hex. However, these bytes will be automatically ...
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... PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION OVERVIEW The ADuC816 incorporates two independent sigma-delta ADCs (Primary and Auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain-gauge, pressure trans- ducer or temperature measurement applications. ...
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... The Auxiliary ADC is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This ADC is not buffered and has a fixed input range 2.5 V THE EXTERNAL REFERENCE INPUT TO THE ADuC816 IS DIFFERENTIAL AND OPERATION. THE EXTERNAL REFER- ENCE VOLTAGE IS SELECTED VIA THE ANALOG INPUT CHOPPING XREF1 BIT IN ADC1CON ...
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PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables IX, X and XI below show the output rms noise in μV and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the ...
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... For example, if AIN(–) is 2.5 V and the primary ADC is config- ured for an analog input range +20 mV, the input voltage range on the AIN(+) input AIN(–) is 2.5 V and the ADuC816 is configured for an analog input range of 1.28 V, the analog input range on the AIN(+) input is 1. 3.78 V (i.e., 2.5 V ± 1.28 V). ...
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... Sigma-Delta Modulator A sigma-delta ADC generally consists of two main blocks, an analog modulator and a digital filter. In the case of the ADuC816 ADCs, the analog modulators consist of a difference amplifier, an integrator block, a comparator, and a feedback DAC as illus- trated in Figure 20. ...
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... The ADuC816 provides four calibration modes that can be pro- grammed via the mode bits in the ADCMODE SFR detailed in Table IV. In fact, every ADuC816 has already been factory calibrated. The resultant Offset and Gain calibration coefficients for both the primary and auxiliary ADCs are stored on-chip in manufacturing-specific Flash/EE memory locations ...
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... IN-CIRCUIT Retention quantifies the ability of the Flash/EE memory to retain REPROGRAMMABLE its programmed data over time. Again, the ADuC816 has been qualified in accordance with the formal JEDEC Retention Life- time Specification (A117 specific junction temperature (T = 55° ...
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... Using the Flash/EE Program Memory The 8 Kbyte Flash/EE Program Memory array is mapped into the lower 8 Kbytes of the 64 Kbytes program space addressable by the ADuC816, and is used to hold user code in typical applications. The program memory Flash/EE memory arrays can be pro- grammed in one of two modes, namely: ...
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... BYTE 1 BYTE 2 BYTE 3 As with other ADuC816 user-peripheral circuits, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) are used to hold 4-byte page data just accessed. EADRL is used to hold the 8-bit address of the page to be accessed. Finally, ECON ...
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... Table XIII. It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation on the ADuC816 is idled until the requested Program/Read or Erase mode is completed. In practice, this means that even though the Flash/EE memory ...
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... The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC816 incorporates a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of DACCON DAC Control Register ...
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... On-Chip PLL The ADuC816 is intended for use with a 32.768 kHz watch crys- tal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency or at binary submultiples allow power saving in cases where maximum core performance is not ...
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... IEIP2 SFR description under Interrupt System later in this data sheet.) If the ADuC816 is in power-down mode, again with TIC interrupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053 hex ...
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TIMECON TIC CONTROL REGISTER SFR Address A1H Power-On Default Value 00H Bit Addressable Bit Name Description 7 --- Reserved for Future Use. 6 --- Reserved for Future Use. For future product code ...
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INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) bit is ...
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... Watchdog Timer The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC816 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The Watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR. When enabled ...
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... Power Supply Monitor As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the ADuC816. It will indicate when any of the supply pins drop below one of four user-selectable voltage trip points from 2. 4.63 V. For correct operation of the Power Supply Monitor function, AV must be equal to or greater than 2 ...
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... SPI peripheral. This line is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC816 to be used in single master, multislave SPI configurations. If CPHA = 1 then the SS input may be permanently pulled low. With CPHA = 0 then the ...
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... SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode. If the ADuC816 needs to assert the SS pin on an external slave device, a Port digital output pin should be used. ...
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... I C-COMPATIBLE INTERFACE The ADuC816 supports a 2-wire serial interface mode which compatible. The I C-compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enable one or the other interface at any given time (see SPE in ...
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... SFR bit definitions. Parallel I/O Ports 0–3 The ADuC816 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations; others are multiplexed with an alternate function for the peripheral features on the device ...
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User configuration and control of all Timer operating modes is achieved via three SFRs namely: TMOD, TCON: Control and configuration for Timers 0 and 1. T2CON: Control and configuration for Timer 2. TMOD Timer/Counter 0 and 1 Mode Register SFR ...
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TCON: Timer/Counter 0 and 1 Control Register SFR Address 88H Power-On Default Value 00H Bit Addressable Yes NOTE These bits are not used in the control of timer/counter 0 and 1, but are used ...
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TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for timer/ counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for timer 0 as for timer ...
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T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes Bit Name Description 7 TF2 Timer 2 Overflow Flag. 6 EXF2 Timer 2 External Flag. EXEN2 = ...
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Timer/Counter 2 Operating Modes The following paragraphs describe the operating modes for timer/ counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXVI. Table XXVI. TIMECON SFR Bit Designations RCLK (or) TCLK ...
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UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive ...
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Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted or ...
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Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: /32) × ...
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... INTERRUPT SYSTEM The ADuC816 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE: Interrupt Enable Register. IP: Interrupt Priority Register. IEIP2: Secondary Interrupt Priority-Interrupt Register. IE: Interrupt Enable Register SFR Address ...
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IEIP2: Secondary Interrupt Enable and Priority Register SFR Address A9H Power-On Default Value A0H Bit Addressable Bit Name Description 7 --- Reserved for Future Use. 6 PTI Written by User to Select ...
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... Single Pin Emulation Mode section of this data sheet. External program memory (if used) must be connected to the ADuC816 as illustrated in Figure 43. Note that 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external program memory fetches. Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the program counter (PCL address, and then goes into a float state awaiting the arrival of the code byte from the program memory ...
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... It emits the low byte of the data pointer (DPL address, which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC816 (write operation) or the SRAM (read operation). Port 2 (P2) provides the data pointer page byte (DPP latched by ALE, followed by the data pointer high byte (DPH) ...
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... Port pins retain their logic levels in this mode, but the DAC output goes to a high-impedance state (three-state) while ALE and PSEN outputs are held low. During full power-down mode the ADuC816 consumes a total of 5 μA typically. There are five ways of terminating power-down mode Asserting the RESET Pin (15) 0 ...
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... ADuC816’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC816 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high-speed signals from coupling capacitively into the ADuC816 and affecting the accuracy of ADC conversions. ...
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... R2OUT Typical System Configuration A typical ADuC816 configuration is shown in Figure 52. It sum- marizes some of the hardware considerations discussed in the previous paragraphs. Figure 52 also includes connections for a typical analog measure- ment application of the ADuC816, namely an interface to an RTD (Resistive Temperature Device). The arrangement shown is commonly referred 4-wire RTD configuration ...
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... QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC816. The system consists of the following PC-based (Windows-compatible) hard- ware and software development tools. Hardware: ...
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... ADuC816BSZ-REEL –40°C to +85°C ADuC816BCPZ –40°C to +85°C ADuC816BCPZ-REEL –40°C to +85° RoHS Compliant Part. ©2001–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...