AD9864 Analog Devices, AD9864 Datasheet - Page 37

• Manufacturer Part Number: AD9864
• Description: IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9864

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 18MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

SPURIOUS RESPONSES
The spectral purity of the LO (including its phase noise) is an
important consideration since LO spurs can mix with unde-
sired signals present at the AD9864’s IFIN input to produce an
in-band response. To demonstrate the low LO spur level intro-
duced within the AD9864, Figure 69 plots the demodulated
output power as a function of the input IF frequency for an LO
frequency of 71.1 MHz and a clock frequency of 18 MHz.
The two large –10 dBFS spikes near the center of the plot are
the desired responses at f
at 68.85 MHz and 73.35 MHz. LO spurs at f
result in spurious responses at offsets of ± f
desired responses. Close-in spurs of this kind are not visible on
the plot, but small spurious responses at f
at 50.85 MHz, 55.35 MHz, 86.85 MHz, and 91.35 MHz, are
visible at the –90 dBFS level. This data indicates that the
AD9864 does an excellent job of preserving the purity of the LO
signal.
Figure 69 can also be used to gauge how well the AD9864
rejects undesired signals. For example, the half-IF response (at
69.975 MHz and 72.225 MHz) is approximately –100 dBFS,
Figure 69. Response of AD9864 to a –20 dBm IF Input when f
–100
–120
–50
–60
–70
–80
–90
–20
–40
–60
–80
70.0
0
50
Figure 68. Expanded View from 70 MHz to 71 MHz
RESPONSES
DESIRED
60
LO FREQUENCY (MHz)
IF FREQUENCY (MHz)
LO
70
, ± f
IF2_ADC
70.5
D =
f
CLK
, where f
80
/4 = 4.5MHz
LO
SPUR
LO
± f
IF2_ADC
± f
90
IF2_ADC
around the
SPUR
= f
LO
would
± f
= 71.1 MHz
CLK
71.0
CLK
100
/8, i.e.,
, i.e.,
Rev. 0 | Page 37 of 44
giving a selectivity of 90 dB for this spurious response. The
largest spurious response at approximately –70 dBFS occurs
with input frequencies of 70.35 MHz and 71.85 MHz. These
spurs result from third order nonlinearity in the signal path
(i.e., abs [3 × f
EXTERNAL PASSIVE COMPONENT REQUIREMENTS
Figure 70 shows an example circuit using the AD9864 and
Table 19 shows the nominal dc bias voltages seen at the differ-
ent pins. The purpose is to show the various external passive
components required by the AD9864, along with nominal dc
voltages for troubleshooting purposes.
100pF
Table 19. Nominal DC Bias Voltages
Pin Number
1
2
4
5
11
12
13
19
20
35
41
42
43
44
46
47
Figure 70. Example Circuit Showing Recommended Component Values
50Ω
180pF
100pF
10nF
100pF
2.2nF
100
pF
LO
10
11
12
1
2
3
4
5
6
7
8
9
– 3 × f
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
VREFN
100kΩ
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
Mnemonic
MXOP
MXON
IF2N
IF2P
VREFP
VREFN
RREF
CLKP
CLKN
FREF
CXVM
LON
LOP
CXVL
CXIF
IFIN
IF_INPUT
] = f
AD9864
CLK
10nF
/8).
10nF
Nominal DC Bias (V)
VDDI – 0.2
VDDI – 0.2
1.3 – 1.7
1.3 – 1.7
VDDA/2 + 0.250
VDDA/2 – 0.250
1.2
VDDC – 1.3
VDDC – 1.3
VDDC/2
1.6 – 2.0
1.65 – 1.9
1.65 – 1.9
VDDI – 0.05
1.6 – 2.0
0.9 – 1.1
CLKOUT
SYNCB
DOUTB
DOUTA
GNDH
GNDL
GNDS
VDDH
VDDD
FREF
PE
FS
AD9864
36
35
34
33
32
31
30
29
28
27
26
25