AD9864 Analog Devices, AD9864 Datasheet - Page 21

• Manufacturer Part Number: AD9864
• Description: IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9864

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 18MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

Table 9. Number of Bits per Frame for Different SSICR Settings
DW
0 (16 Bit)
1 (24 Bit)
*The number of bits per frame with embedded frame sync (EFS = 1); assume
The maximum SSIORD setting can be determined by the
equation
where TRUNC is the truncated integer value.
Table 9 lists the number of bits within a frame for 16-bit and 24-
bit output data formats for all of the different SSICR settings. The
decimation factor is determined by the contents of Register 0x07.
An example helps illustrate how the maximum SSIORD setting
is determined. Suppose a user selects a decimation factor of 600
(Register 0x07, K = 0, M = 9) and prefers a 3-wire interface with
a dedicated frame sync (EFS = 0) containing 24-bit data
(DW = 1) with nonalternating embedded AGC data included
(EAGC = 1, AAGC = 0). Referring to Table 9, each frame will
consist of 64 data bits. Using Equation 1, the maximum
SSIORD setting is 9 (= TRUNC(600/64)). Thus, the user can
select any SSIORD setting between 1 and 9.
Figure 32 illustrates the output timing of the SSI port for several
SSI control register settings with 16-bit I/Q data, while Figure 33
shows the associated timing parameters. Note that the same
timing relationship holds for 24-bit I/Q data, with the excep-
tion that I and Q word lengths now become 24 bits. In the
default mode of operation, data is shifted out on rising edges of
CLKOUT after a pulse equal to a clock period is output from
the frame sync (FS) pin. As described above, the output data
consists of a 16-bit or 24-bit I sample followed by a 16-bit or
24-bit Q sample, plus two optional bytes containing AGC and
status information.
at least 10 idle bits are desired.
SSIORD
≤
EAGC
0
0
1
1
1
1
0
0
1
1
1
1
TRUNC
[
(
Decimation
EFS
0
1
0
0
1
1
0
1
0
0
1
1
Factor
) (
/
No.
AAGC
NA
NA
0
1
0
1
NA
NA
0
1
0
1
of
Bits
per
Frame
Number
of Bits
per
Frame
32
49*
48
40
69*
59*
48
69*
64
56
89*
79*
)
]
(1)
Rev. 0 | Page 21 of 44
*Timing parameters also apply to inverted CLKOUT or FS modes, with t
The AD9864 also provides the means for controlling the
switching characteristics of the digital output signals via the DS
(drive strength) field of the SSICRB. This feature is useful in
limiting switching transients and noise from the digital output
that may ultimately couple back into the analog signal path,
potentially degrading the AD9864’s sensitivity performance.
Figure 34 and Figure 35 show how the NF can vary as a func-
tion of the SSI setting for an IF frequency of 109.65 MHz. The
following two observations can be made from these figures:
1. The NF becomes more sensitive to the SSI output drive
2.
relative to the falling edge of the CLK and/or FS.
strength level at higher signal bandwidth settings.
The NF is dependent on the number of bits within an SSI
frame that become more sensitive to the SSI output drive
strength level as the number of bits is increased. As a result,
one should select the lowest possible SSI drive strength set-
ting that still meets the SSI timing requirements.
10.0
9.2
8.2
9.8
9.6
9.4
9.0
8.8
8.6
8.4
8.0
CLKOUT
1
DOUT
Figure 33. SSI Timing Parameters for SSI Timing*
FS
(VDDx = 3.0 V, F
Figure 34. NF vs. SSI Output Drive Strength
2
SSI OUTPUT DRIVE STRENGTH SETTING
t
HI
t
t
16-BIT I/O DATA
CLK
DV
t
V
t
LOW
3
24-BIT I/O DATA
CLK
= 18 MSPS, BW = 10 kHz)
4
I15
5
w/ DVGA ENABLED
I14
16-BIT I/0 DATA
6
AD9864
7
DV