AD7329 Analog Devices, AD7329 Datasheet - Page 7

• Manufacturer Part Number: AD7329
• Description: 1 MSPS , 8-Channel, Software Selectable True Bipolar Input, 12-Bit Plus Sign A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7329

• Resolution (bits): 13bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref),Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 2.5V,Bip 5.0V,Uni (Vref),Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

TIMING SPECIFICATIONS
V
T
connected directly to ADC
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
10
POWER-UP
When using V
MIN
1
DD
= 12 V to 16.5 V, V
. Timing specifications apply with a 32 pF load, unless otherwise noted. MUX
CC
= 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t
V
50
14
16 × t
75
12
25
45
26
57
0.4 × t
0.4 × t
13
40
10
4
2
750
500
25
CC
DOUT
SCLK
< 4.75 V
DIN
CS
SCLK
SCLK
SCLK
THREE-
STATE
SS
Limit at T
= −12 V to −16.5 V, V
WRITE
ADD2
IN
t
2
−, which is connected to GND for single-ended mode.
1
3 IDENTIFICATION BITS
t
ADD1
V
50
20
16 × t
60
5
20
35
14
43
0.4 × t
0.4 × t
8
22
9
4
2
750
500
25
3
CC
t
SEL1
REG
9
MIN
= 4.75 V to 5.25 V
2
, T
SCLK
SCLK
SCLK
ADD0
MAX
SEL2
REG
3
SIGN
CC
MSB
= 4.75 V to 5.25 V, V
4
Figure 2. Serial Interface Timing Diagram
DB11
t
t
6
4
t
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
μs typ
CONVERT
t
10
5
t
DB10
7
Rev. A | Page 7 of 40
V
Unipolar input range (0 V to 10 V)
SCLK falling edge to DOUT high impedance
DIN hold time after SCLK falling edge
Description
t
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
Power-up from autostandby
Power-up from full shutdown/autoshutdown mode, internal
reference
Power-up from full shutdown/autoshutdown mode, external
reference
SCLK
DRIVE
DRIVE
13
= 1/f
DB2
≤ V
= 2.7 V to 5.25 V, V
SCLK
CC
14
t
5
DB1
OUT
LSB
+ is connected directly to ADC
15
DB0
2
at 20 ns, the mark-space ratio must be limited to 50:50.
0
16
THREE-STATE
REF
t
8
= 2.5 V internal/external, T
t
QUIET
t
1
IN
+ and MUX
A
AD7329
= T
OUT
MAX
− is
to