AD7329 Analog Devices, AD7329 Datasheet - Page 33

• Manufacturer Part Number: AD7329
• Description: 1 MSPS , 8-Channel, Software Selectable True Bipolar Input, 12-Bit Plus Sign A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7329

• Resolution (bits): 13bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref),Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 2.5V,Bip 5.0V,Uni (Vref),Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
When the autoshutdown mode is selected, the AD7329
automatically enters shutdown on the 15
autoshutdown mode, all internal circuitry is powered down.
The AD7329 retains information in the registers during
autoshutdown. The track-and-hold section is in hold mode
during autoshutdown. On the rising CS edge, the track-and-
hold section, which was in hold during shutdown, returns to
track as the AD7329 begins to power up. The time to power up
from autoshutdown is 500 μs.
When the control register is programmed to transition to
autoshutdown mode, it does so on the 15
Figure 54 shows the part entering autoshutdown mode. The
AD7329 automatically begins to power up on the CS rising
edge. The t
by bringing the CS signal low, can take place. After this valid
conversion is complete, the AD7329 powers down again on the
15
keep the part in autoshutdown mode.
th
SDATA
SCLK rising edge. The CS signal must remain low again to
SCLK
DIN
CS
POWER-UP
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS
1
is required before a valid conversion, initiated
DATA INTO CONTROL REGISTER
PART ENTERS SHUTDOWN MODE
ON THE 15
IF PM1 = 1, PM0 = 0
PM1 = 1, PM0 = 0
VALID DATA
TH
th
RISING SCLK EDGE
th
SCLK rising edge. In
SCLK rising edge.
Figure 54. Entering Autoshutdown/Autostandby Mode
15
PART BEGINS TO POWER
UP ON CS RISING EDGE
16
Rev. A | Page 33 of 40
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7329 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to
autoshutdown but allows the AD7329 to power up much faster,
which allows faster throughput rates.
As is the case with autoshutdown mode, the AD7329 enters
standby on the 15
is updated (see Figure 54). The part retains information in the
registers during standby. The AD7329 remains in standby until
it receives a CS rising edge. The ADC begins to power up on the
CS rising edge. On the CS rising edge, the track-and-hold,
which was in hold mode while the part was in standby, returns
to track.
The power-up time from standby is 750 ns. The user should
ensure that 750 ns have elapsed before bringing CS low to
attempt a valid conversion. After this valid conversion is
complete, the AD7329 again returns to standby on the 15
SCLK rising edge. The CS signal must remain low to keep the
part in standby mode.
Figure 54 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby
mode. In Figure 54, the power management bits are configured
for autoshutdown. For autostandby mode, the power
management bits, PM1 and PM0, should be set to 0 and 1,
respectively.
t
POWER-UP
THE PART IS FULLY POWERED UP
ONCE
t
POWER-UP
1
th
SCLK rising edge when the control register
HAS ELAPSED
DATA INTO CONTROL REGISTER
VALID DATA
15
AD7329
16
th