AD7984 Analog Devices, AD7984 Datasheet - Page 5
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AD7984
Manufacturer Part Number
AD7984
Description
18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN
Manufacturer
Analog Devices
Datasheet
1.AD7984.pdf
(24 pages)
Specifications of AD7984
Resolution (bits)
18bit
# Chan
1
Sample Rate
1.33MSPS
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p
Adc Architecture
SAR
Pkg Type
CSP,SOP
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Quantity:
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Company:
Part Number:
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Manufacturer:
ADI
Quantity:
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Manufacturer:
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Quantity:
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TIMING SPECIFICATIONS
T
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1
See Figure 2 and Figure 3 for load conditions.
A
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 3 V
VIO Above 2.3 V
= −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.
Figure 2. Load Circuit for Digital Interface Timing
TO SDO
20pF
C
L
500µA
500µA
I
I
OL
OH
1.4V
Rev. A | Page 5 of 24
1
2
FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
MINIMUM V
SPECIFICATIONS IN TABLE 3.
X% VIO
t
DELAY
1
IH
AND MAXIMUM V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CONV
ACQ
CYC
CNVH
SCK
SCK
SCKL
SCKH
HSDO
DSDO
EN
DIS
SSDICNV
HSDICNV
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
Figure 3. Voltage Levels for Timing
1
V
V
IH
IL
2
2
IL
Min
300
250
750
10
10.5
12
13
15
11.5
13
14
16
4.5
4.5
3
5
2
0
5
5
2
3
USED. SEE DIGITAL INPUTS
Typ
Y% VIO
t
1
DELAY
V
V
IH
IL
2
2
Max
500
9.5
11
12
14
10
15
20
15
AD7984
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns