AD7984 Analog Devices, AD7984 Datasheet - Page 22

• Manufacturer Part Number: AD7984
• Description: 18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN
• Manufacturer: Analog Devices

Specifications of AD7984

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 1.33MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7984
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7984s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7984s is shown
in Figure 38, and the corresponding timing is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
ACQUISITION
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
A
B
C
C
CONVERSION
t
SDI
t
DSDOSDI
t
SSCKCNV
t
CONV
DSDOSDI
t
EN
AD7984
CNV
SCK
A
t
t
t
SSDISCK
HSDO
DSDO
1
D
D
SDO
D
C
A
B
2
17 D
17 D
17 D
Figure 39. Chain Mode with Busy Indicator Serial Interface Timing
Figure 38. Chain Mode with Busy Indicator Connection Diagram
C
A
B
3
16 D
16 D
16 D
t
SCKH
SDI
C
A
B
4
t
HSDISCK
15
15
15
AD7984
17
CNV
SCK
t
SCK
B
Rev. A | Page 22 of 24
D
D
D
18
C
B
A
1
1
1
t
SDO
SCKL
D
D
D
19
C
B
A
0
0 D
0
D
ACQUISITION
20
B
A
17 D
17 D
t
CYC
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7984 ADC labeled C in Figure 38) is
driven high. This transition on SDO can be used as a busy indicator
to trigger the data readback controlled by the digital host. The
AD7984 then enters the acquisition phase and goes into standby
mode. The data bits stored in the internal shift register are clocked
out, MSB first, by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 18 × N + 1 clocks are required to read back the N
ADCs. Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7984s in the chain, provided
the digital host has an acceptable hold time.
SDI
21
B
A
t
16
16
ACQ
AD7984
CNV
SCK
35
C
D
D
36
B
A
1
1
SDO
D
D
37
B
A
0 D
0
38
A
17
CONVERT
DATA IN
CLK
IRQ
D
DIGITAL HOST
39
A
16
53
t
DSDOSDI
D
54
t
A
DSDOSDI
t
1
DSDOSDI
D
55
A
0