AD7984 Analog Devices, AD7984 Datasheet - Page 21

• Manufacturer Part Number: AD7984
• Description: 18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN
• Manufacturer: Analog Devices

Specifications of AD7984

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 1.33MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7984s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7984s is shown in
Figure 36, and the corresponding timing is given in Figure 37.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
SDO
ACQUISITION
SDI
A
t
HSCKCNV
= SDI
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
Figure 37. Chain Mode Without Busy Indicator Serial Interface Timing
AD7984
Figure 36. Chain Mode Without Busy Indicator Connection Diagram
D
D
CNV
SCK
1
A
B
A
17
17
t
SSDISCK
D
D
2
A
B
SDO
16
16
D
D
3
A
B
15
15
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t
SCKL
t
SDI
HSDISCK
16
AD7984
CNV
SCK
t
B
D
D
17
CYC
A
B
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7984 enters the acquisition phase and
goes into standby mode. The remaining data bits stored in the
internal shift register are clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first, and 18 × N clocks are
required to read back the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7984s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
1
1
ACQUISITION
t
SCK
t
SCKH
t
D
D
SDO
ACQ
18
A
B
0
0
D
19
A
17
CONVERT
DATA IN
CLK
DIGITAL HOST
D
20
A
16
34
D
35
A
1
D
36
A
0
AD7984