SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 453
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SAM3A8C
Manufacturer Part Number
SAM3A8C
Description
Manufacturer
Atmel Corporation
- Current page: 453 of 1465
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Figure 26-20. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip
Figure 26-21. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
read1 controlling signal
read2 controlling signal
write2 controlling signal
read1 controlling signal
NBS0, NBS1,
NBS0, NBS1,
A[ 23:2]
D[15:0]
A0, A1
(NRD)
(NRD)
A [23:2]
D[15:0]
A0, A1
(NWE)
selects
(NRD)
MCK
MCK
TDF_CYCLES = 6
TDF_CYCLES = 4
read1 cycle
read1 cycle
read1 hold = 1
read1 hold = 1
Chip Select Wait State
TDF_CYCLES = 4
Read to Write
Wait State
TDF_CYCLES = 6
Chip Select
Wait State
2 TDF WAIT STATES
5 TDF WAIT STATES
write2 setup = 1
(optimization disabled)
TDF_MODE = 0
write2 cycle
(optimization disabled)
SAM3X/A
SAM3X/A
TDF_MODE = 0
read2 setup = 1
read 2 cycle
453
453
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