SAM9XE256 Atmel Corporation, SAM9XE256 Datasheet - Page 218
SAM9XE256
Manufacturer Part Number
SAM9XE256
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE256
Flash (kbytes)
256 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 218 of 248
- Download datasheet (2Mb)
CP15 Test and Debug Registers
B.1.5
B-12
Cache Debug Control Register
31
The data to be written or read is placed in ARM register Rd with the format shown in
Figure B-4 on page B-8.
The Cache Debug Control Register is used to force specific cache behavior required for
debug.
The following instructions can be used to access the Cache Debug Control Register:
The Cache Debug Control Register format is shown in Figure B-7.
The Cache Debug Control Register bit assignments are listed in Table B-9. The reset
value of the Cache Debug Control Register is
Bit
[31:3]
[2]
[1]
[0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
Name
-
DWB
DIL
DDL
Function
Reserved
Disable write-back (force WT)
Disable ICache linefill
Disable DCache linefill
Table B-9 Cache Debug Control Register bit assignments
SBZ
Figure B-7 Cache Debug Control Register format
.
Description
Read = Unpredictable
Write = Should Be Zero
0 = Enable write-back behavior
1 = Force write-through behavior
0 = Enable ICache linefills
1 = Disable ICache linefills
0 = Enable DCache linefills
1 = Disable DCache linefills
DWB
DDL
DIL
ARM DDI0198D
3
2
1
0
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