SAM9XE256 Atmel Corporation, SAM9XE256 Datasheet - Page 136
SAM9XE256
Manufacturer Part Number
SAM9XE256
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE256
Flash (kbytes)
256 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 136 of 248
- Download datasheet (2Mb)
Tightly-Coupled Memory Interface
5-28
This is similar to the previous DMA example. However, for BIST testing it is necessary
for the BIST controller to be able to force the memory chip select to both HIGH and
LOW values. This requirement means that it is necessary to hold the ARM926EJ-S core
in such a state that the internal value of the chip select is guranteed to be LOW. This can
be done by holding the ARM926EJ-S in reset (HRESETn LOW) during TCM memory
BIST testing. Note that this requires that HRESETn cannot also be used as a reset
control to the BIST controller.
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRDMAADDR[17:0]
DRADDR[17:0]
ARM926EJ-S
HRESETn
DRWD[31:0]
DRWBL[3:0]
DRDMAEN
DRDMACS
DRWAIT
DRSEQ
DRnRW
DRCS
Figure 5-19 TCM test access using BIST
1
0
1
0
1
0
BISTADDR[17:0]
BISTEN
BISTCS
BISTWD[31:0]
BISTnRW
BISTWBL[3:0]
BISTRD[31:0]
BISTRSTn
RD[31:0]
WBL[3:0]
nRW
WD[31:0]
A[17:0]
CS
ARM DDI0198D
BIST
SRAM
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