SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 80
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 80 of 248
- Download datasheet (2Mb)
Memory Management Unit
3.2.9
3-16
Translating large page references
The two least significant bits of the second-level descriptor indicate the descriptor type
as shown in Table 3-8.
Tiny pages do not support subpage permissions and therefore only have one set of
access permission bits.
Figure 3-10 on page 3-17 shows the complete translation sequence for a 64KB large
page.
Bits
Large
[11:4]
[3:2]
[1:0]
Value
0 0
0 1
1 0
1 1
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Small
[11:4]
[3:2]
[1:0]
Meaning
Invalid
Large page
Small page
Tiny page
Tiny
[5:4]
[3:2]
[1:0]
Access permission bits. Domain access control on page 3-24
These bits indicate the page size and validity and are
Description
and Fault checking sequence on page 3-26 show how to
interpret the access permission bits.
These bits, C and B, indicate whether the area of memory
mapped by this page is treated as write-back cachable,
write-through cachable, noncached buffered, or noncached
nonbuffered.
interpreted as shown in Table 3-8.
Table 3-7 Second-level descriptor bits (continued)
Table 3-8 Interpreting page table entry bits [1:0]
Description
Generates a page translation fault
Indicates that this is a 64KB page
Indicates that this is a 4KB page
Indicates that this is a 1KB page
ARM DDI0198D
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