SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 248
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 248 of 248
- Download datasheet (2Mb)
Index
Stall cycles 5-29, 5-30
Status field 2-19
Subpages 3-20
Synchronizing data and instruction
System control coprocessor registers
System protection 2-14
T
TCM
TCM interface
TCM status register 2-7
Test and clean
Test and debug register 2-36
Test registers B-2
Test, clean, and invalidate DCache
Thumb instruction fetches 6-6
Timing diagram conventions xviii
Tiny page references, translating 3-19
TLB
TLB operations register 2-24
Trace control register B-5
Trace port 10-2
Transfer size 6-3
Translated entries 3-3
Translating page tables 3-7
Translation fault 3-27
Translation table base 3-6
Trigering facilities 10-2
TTB 3-6
Typographical conventions xviii
Index-4
access priorities 4-8
optimizing for power 5-22
optimizing for speed 5-23
region register 2-26
region register, using 5-19
status register 2-7, 2-12
examples 5-20
signals A-14
DCache 2-21
operations 2-24
lockdown register 2-32
operations 2-25
structure 3-31
register 2-17
streams 9-3
2-3
2-21
Copyright © 2001-2003 ARM Limited. All rights reserved.
U
UND 2-5
Undefined 2-5
Unified or separate cache 2-9
Unlock procedure 2-29
UNP 2-5
Unpredictable 2-5
V
V bit 2-14
VA 2-4
Victim field 2-32
Virtual address 2-4
W
Wait for interrupt 2-22
Wait for interrupt mode 12-2
Write buffer 4-4
Writeback (WB)
Write-through (WT)
Z
Zero-wait-state RAM 5-20
C and B bits 4-2
caches 4-2
C and B bits 4-2
cache operation 4-2
caches 4-2
ARM DDI0198D
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