SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 117
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 117 of 248
- Download datasheet (2Mb)
5.3.1
ARM DDI0198D
Zero wait state timing
IRADDR
IRSEQ
IRRD
IRCS
CLK
For zero wait state accesses the timing of the TCM interface corresponds to the timing
of a standard SRAM component, with minimal interfacing logic required. Figure 5-2
shows examples of zero wait state accesses on the ITCM interface corresponding to
instruction fetches. All accesses are reads.
In cycle T1, a nonsequential request is made to address A.
In cycle T2, a sequential request is made to A+1 and data for the access to A is returned.
In cycle T3, no request is made and data is returned for the access to A+1
In cycle T4, a sequential request is made to A+2.
In cycle T5, a nonsequential request is made to address B and data is returned for the
access to A+2.
In cycle T6, a nonsequential request is made to address C and data is returned for the
access to B
It is important to note that, for the ITCM interface, cycles of a sequential request cycle
do not necessarily occur in consecutive bus cycles. Any number of idle request cycles
can occur between two requests, with the second request being marked as being
sequential. The DTCM interface only produces sequential requests during consecutive
bus cycles.
Figure 5-3 on page 5-10 shows examples of data side zero wait state accesses.
Copyright © 2001-2003 ARM Limited. All rights reserved.
T1
A
T2
A+1
I(A)
T3
Figure 5-2 Instruction side zero wait state accesses
I(A+1)
T4
A+2
T5
B
I(A+2)
Tightly-Coupled Memory Interface
T6
C
I(B)
T7
I(C)
5-9
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