SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 118
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 118 of 248
- Download datasheet (2Mb)
Tightly-Coupled Memory Interface
5.3.2
5-10
DMA access to zero wait state TCM
DRADDR
DRWBL
DRSEQ
DRWD
DnRW
DRCS
DRRD
CLK
In cycle T1, a nonsequential read request is made to address A.
In cycle T2, a nonsequential word write request is made to address B and data is
returned for the access to A.
In cycle T3, no request is made.
In cycle T4, a nonsequential read request is made to address C.
In cycle T5, a sequential read request is made to address C+1 and data is returned for
the access to C.
In cycle T6, a nonsequential byte write request is made to address D.
For DMA accesses to zero wait state memories, the TCM DMA interface can be used
which enables an alternative source of address and chip-select to be passed through to
the TCM memories without impacting timing. Figure 5-4 on page 5-11 shows the
relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and
DRCS.
Copyright © 2001-2003 ARM Limited. All rights reserved.
T1
A
0000
T2
B
D(B)
1111
D(A)
T3
Figure 5-3 Data side zero wait state accesses
T4
C
0000
T5
C+1
D(C)
T6
D
D(D)
D(C+1)
0001
ARM DDI0198D
T7
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