SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 49
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SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 49 of 284
- Download datasheet (2Mb)
2.2
2.2.1
ARM DDI 0029G
Processor operating states
Switching state
The ARM7TDMI processor has two operating states:
ARM
Thumb
In Thumb state, the Program Counter (PC) uses bit 1 to select between alternate
halfwords.
Transition between ARM and Thumb states does not affect the processor mode or the
register contents.
The operating state of the ARM7TDMI core can be switched between ARM state and
Thumb state using the BX instruction. This is described in the ARM Architecture
Reference Manual.
All exception handling is entered in ARM state. If an exception occurs in Thumb state,
the processor reverts to ARM state. The transition back to Thumb state occurs
automatically on return. An exception handler can change to Thumb state but it must
return to ARM state to allow the exception handler to terminate correctly.
Note
Copyright © 1994-2001. All rights reserved.
32-bit, word-aligned ARM instructions are executed in this state.
16-bit, halfword-aligned Thumb instructions are executed in this state.
Programmer’s Model
2-3
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