SAM9R64 Atmel Corporation, SAM9R64 Datasheet
SAM9R64
Specifications of SAM9R64
Related parts for SAM9R64
SAM9R64 Summary of contents
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... Battery Backup Power Supply, Providing a Permanent Slow Clock – 12 MHz On-chip Oscillator for Main System Clock and USB Clock – One PLL up to 240 MHz ® ® ARM Thumb Processor ® Acceleration o 2048x2048, Vir AT91SAM ARM-based Embedded MPU AT91SAM9R64 AT91SAM9RL64 tual Screen 6289D–ATARM–3-Oct-11 ...
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... One Four-channel 16-bit PWM Controller (PWMC) • Two Two-wire Interfaces (TWI) – Compatible with Standard Two-wire Serial Memories – One, Two or Three Bytes for Slave Address – Sequential Read/Write Operations AT91SAM9R64/RL64 2 ™ 4.3 Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding 6289D–ATARM–3-Oct-11 ...
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... Some features are not available for AT91SAM9R64 in the 144-ball BGA package. Separate block diagrams and PIO multiplexing are provided in this document. features and signals of AT91SAM9RL64 that are not available or partially available for AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified. Table 1-1. Feature ...
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... Table 1-1. Feature PWM SPI SSC1 Touchscreen ADC TC TWI USART0 USART1 USART2 USART3 AT91SAM9R64/RL64 4 Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Signal Partial PWM2 NPCS2 Partial NPCS3 RF1 RK1 TD1 Full RD1 TK1 TF1 AD3YM Partial GPAD4 GPAD5 TIOA1 TIOB1 Partial ...
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... Block Diagrams Figure 2-1. AT91SAM9R64 Block Diagram 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 5 ...
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... Figure 2-2. AT91SAM9RL64 Block Diagram AT91SAM9R64/RL64 6 6289D–ATARM–3-Oct-11 ...
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... Output Analog Input Output Shutdown, Wakeup Logic Output Input ICE and JTAG Input Input Output Input Input AT91SAM9R64/RL64 Comments 1.65V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 1.08V to 1.32V 3.0V to 3.6V 1. 1.32V 3.0V to 3.6V 1.08V to 1.32V Driven at 0V only. 0: The device is in backup mode. 1: The device is running (not in backup mode.) ...
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... BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset. D16-D31 not present on AT91SAM9R64 reset NCS2, NCS5 not present on AT91SAM9R64. CFCS1 not present on AT91SAM9R64. 6289D–ATARM–3-Oct-11 ...
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... CTS0, CTS2, CTS3 not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. TD1 not present on AT91SAM9R64. RD1 not present on AT91SAM9R64. TK1 not present on AT91SAM9R64. RK1 not present on AT91SAM9R64. TF1 not present on AT91SAM9R64. RF1 not present on AT91SAM9R64. 9 ...
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... Not present on AT91SAM9R64. TCLK1 not present on AT91SAM9R64. TIOA1, TIOA2 not present on AT91SAM9R64. TIOB1, TIOB2 not present on AT91SAM9R64. PWM2 not present on AT91SAM9R64. NPCS2, NPCS3 not present on AT91SAM9R64. TWD1 not present on AT91SAM9R64. TWCK1 not present on AT91SAM9R64. GPAD4, GPAD5 not present on AT91SAM9R64. Multiplexed with AD0 ...
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... DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Active Type Level Comments USB High Speed Device Analog Analog Analog Analog ...
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... Package and Pinout The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available in a 217-ball LFBGA package. 4.1 144-ball BGA Package Outline Figure 4-1 Figure 4-1. 144-ball BGA Pinout (Top View) AT91SAM9R64/RL64 12 shows the orientation of the 144-ball BGA package ...
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... Pinout Table 4-1. AT91SAM9R64 Pinout for 144-ball BGA Package Pin Signal Name Pin A1 DFSDM D1 A2 DHSDM D2 A3 XIN D3 A4 XOUT D4 A5 XIN32 D5 A6 XOUT32 D6 A7 TDO D7 A8 PA[31 PA[22] D9 A10 PA[16] D10 A11 PA[14] D11 A12 PA[11] D12 B1 DFSDP E1 B2 DHSDP VDDPLLB E4 B5 GNDPLLB ...
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... LFBGA Package Outline Figure 4-2 Figure 4-2. 217-ball LFBGA Pinout (Top View) AT91SAM9R64/RL64 14 shows the orientation of the 217-ball LFBGA package BALL A1 6289D–ATARM–3-Oct-11 ...
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... PB[ PB[ VDDCORE P3 H9 VDDIOP P4 H10 PD[4] P5 H14 PD[8] P6 H15 PD[5] P7 H16 PD[2] P8 H17 PD[ PB[12] P10 J2 PB[13] P11 J3 PB[11] P12 J4 PB[10] P13 J8 VDDCORE P14 J9 VDDIOP P15 J10 PC[29] P16 AT91SAM9R64/RL64 (1) Signal Name Pin PD[1] P17 PD[0] R1 PC[30] R2 PC[31] R3 PB[14] R4 PB[15] R5 PB[17] R6 PB[16] R7 VDDUTMIC R8 VDDIOP R9 PC[28] R10 PC[25] R11 PC[24] R12 PC[26] R13 PC[27] R14 PB[18] R15 PB[19] R16 PB[21] R17 PB[20] T1 PC[21] T2 PC[20] T3 PC[22] T4 ...
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... Power Considerations 5.1 Power Supplies The AT91SAM9R64/RL64 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). • ...
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... MHz with 50 pF load. 6289D–ATARM–3-Oct-11 Example of PLL and USB Power Supplies VIN VOUT CE 10µF VSS MIC5235YM5 2.2µH 1V2_USB 2.2µH 1V2_USB 2.2µH 3V3 AT91SAM9R64/RL64 10µF 0.1µF 1K ADJ 100K VDDPLLB 0.1µF VDDUTMIC 0.1µF VDDUTMII 0.1µF 1V2_USB 17 ...
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... PIO Controllers All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product datasheet for more details. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “ ...
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... Matrix Masters The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 masters, which means that each master can perform an access concurrently with others available slave. Each master has its own decoder, which is defined specifically for each master. In order to sim- plify the addressing, all the masters have the same decodings. ...
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... Table 7-1. Master 3 Master 4 Master 5 7.3 Matrix Slaves The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 7.4 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “ ...
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... Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 6289D–ATARM–3-Oct-11 USART0 Transmit Channel SSC1 Transmit Channel SSC0 Transmit Channel DBGU Receive Channel AC97 Receive Channel SSC1 Receive Channel AT91SAM9R64/RL64 21 ...
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... Memories Figure 8-1. AT91SAM9R64/RL64 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes Chip Select 2 ...
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... Notes: 8.1.1.1 Internal SRAM The AT91SAM9R64/RL64 product embeds a total of 64Kbyte high-speed SRAM split in 4 blocks of 16KBytes. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. ...
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... RB2 SRAM C 0x0030 8000 RB1 (AHB) 0x0030 C000 RB0 Note: 1. Configuration after reset. AT91SAM9R64/RL64 24 0 16K Bytes 32K Bytes illustrates different configurations and the related 16-Kbyte blocks (RB0 to RB3) Configuration examples and related 16-Kbyte block assignments I = 16K I =32K ...
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... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The AT91SAM9R64/RL64 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect ...
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... Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock • Switch the main clock to the new value 8.2 External Memories The AT91SAM9R64/RL64 features one External Bus Interface to offer interface to a wide range of external memories and to any parallel peripheral. 8.2.1 External Bus Interface • Integrates three External Memory Controllers: – ...
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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 6289D–ATARM–3-Oct-11 detected erroneous pages AT91SAM9R64/RL64 27 ...
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... However, all the registers of System Controller are mapped on the top of the address space. This allows addressing all the registers of the System Controller from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of +/- 4kbytes. AT91SAM9R64/RL64 28 Figure 8-1, the System Controller’s peripherals are all mapped within the highest ...
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... MAINCK PCK Power Management MCK Controller HSCK pmc_irq idle PLLACK periph_irq[2..4] irq dbgu_rxd PIO fiq Controllers dbgu_txd AT91SAM9R64/RL64 nirq nfiq ntrst ARM926EJ-S por_ntrst proc_nreset PCK debug jtag_nreset Boundary Scan TAP Controller MCK Bus Matrix periph_nreset HSCK periph_clk[22] USB High Speed ...
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... One 80 to 240 MHz programmable PLL, providing the PLL Clock (PLLCK). This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 1 MHz. AT91SAM9R64/RL64 30 6289D–ATARM–3-Oct-11 ...
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... Slow Clock Selection 9.6.1 Description The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external slow clock on XIN32. Configuration is located in the slow clock control register (SCKCR) located at address 0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is present. Refer to the “ ...
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... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9R64/RL64 Power Management Controller Block Diagram Master Clock Controller SLCK MAINCK PLLCK 9 ...
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... Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes 6289D–ATARM–3-Oct-11 enabled processor Generator AT91SAM9R64/RL64 33 ...
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... Peripheral Mapping As shown in space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. AT91SAM9R64/RL64 34 the ARM Processor’s ICE Interface Figure 8-1, the Peripherals are mapped in the upper 256M bytes of the address 6289D–ATARM–3-Oct-11 ...
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... DMAC 22 UDPHS 23 LCDC 24 AC97 25- AIC Note: 6289D–ATARM–3-Oct-11 defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral iden- Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D USART 0 USART 1 USART 2 USART 3 Multimedia Card Interface ...
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... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.4 Peripherals Signals Multiplexing on I/O Lines The AT91SAM9R64/RL64 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which mul- tiplexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... RF1 I/O VDDIOP RK1 I/O VDDIOP RK0 I/O VDDIOP I/O VDDIOP I/O VDDIOP TD1 I/O VDDIOP RD1 I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDANA RTS1 I/O VDDANA CTS1 I/O VDDANA SCK3 I/O VDDANA I/O VDDIOP RF0 I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP TF1 I/O VDDIOP TK1 I/O VDDIOP IRQ I/O VDDIOP AT91SAM9R64/RL64 Application Usage Function Comments 37 ...
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... PB20 D20 PB21 D21 PB22 D22 PB23 D23 PB24 D24 PB25 D25 PB26 D26 PB27 D27 PB28 D28 PB29 D29 PB30 D30 PB31 D31 AT91SAM9R64/RL64 38 Reset Power Peripheral B State Supply I/O VDDIOP I/O VDDIOP A21 VDDIOM A22 VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM NPCS1 I/O VDDIOM ...
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... VDDIOP LCDD7 I/O VDDIOP LCDD10 I/O VDDIOP LCDD11 I/O VDDIOP LCDD12 I/O VDDIOP LCDD13 I/O VDDIOP LCDD14 I/O VDDIOP LCDD15 I/O VDDIOP LCDD18 I/O VDDIOP LCDD19 I/O VDDIOP LCDD20 I/O VDDIOP LCDD21 I/O VDDIOP LCDD22 I/O VDDIOP LCDD23 I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP TIOA1 I/O VDDIOP TIOB1 I/O VDDIOP TCLK1 I/O VDDIOP AT91SAM9R64/RL64 Application Usage Function Comments 39 ...
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... TIOB2 PD12 PWM2 PCK1 PD13 NCS5/CFCS1 NPCS3 PD14 DSR0 PWM0 PD15 DTR0 PWM1 PD16 DCD0 PWM2 PD17 RI0 PD18 PWM3 PD19 PCK0 PD20 PCK1 PD21 TCLK2 AT91SAM9R64/RL64 40 Reset Power Comments State Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDANA I/O VDDANA I/O VDDIOP I/O ...
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... AT91SAM9R64 PIO Multiplexing Note: In Table 10-6, Table 10-7, Table 10-8 AT91SAM9R64. 10.4.2.1 AT91SAM9R64 PIO Controller A Multiplexing Table 10-6. AT91SAM9R64 Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 MC_DA0 PA1 MC_CDA PA2 MC_CK PA3 MC_DA1 PA4 MC_DA2 PA5 MC_DA3 PA6 TXD0 PA7 RXD0 PA8 NA PA9 NA PA10 CTS0 ...
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... AT91SAM9R64 PIO Controller B Multiplexing Table 10-7. AT91SAM9R64 Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 TXD3 PB1 RXD3 PB2 A21/NANDALE PB3 A22/NANDCLE PB4 NANDOE PB5 NANDWE PB6 NCS3/NANDCS PB7 NCS4/CFCS0 PB8 CFCE1 PB9 CFCE2 PB10 A25/CFRNW PB11 A18 PB12 A19 PB13 A20 ...
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... AT91SAM9R64 PIO Controller C Multiplexing Table 10-8. AT91SAM9R64 Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 TF0 PC1 TK0 PC2- NA PC31 10.4.2.4 AT91SAM9R64 PIO Controller D Multiplexing Table 10-9. AT91SAM9R64 Multiplexing on PIO Controller D PIO Controller D I/O Line Peripheral A Peripheral B PD0- NA PD17 PD18 PWM3 PD19 PCK0 PD20 PCK1 ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first AT91SAM9R64/RL64 44 peripherals Sensors and data per chip select ...
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... Variable sampling rate AC97 Codec Interface (48KHz and below) 11.6 Timer Counter (TC) • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 2 S, TDM Buses, Magnetic Card Reader, etc.) 45 ...
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... USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver • Embedded 4K-byte dual-port RAM for endpoints • Embedded 6 channels DMA controller • Suspend/Resume logic • banks for isochronous and bulk endpoints • Seven endpoints: AT91SAM9R64/RL64 46 6289D–ATARM–3-Oct-11 ...
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... Multiple trigger sources – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all 6289D–ATARM–3-Oct-11 enabled channels AT91SAM9R64/RL64 47 ...
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... AT91SAM9R64/RL64 48 6289D–ATARM–3-Oct-11 ...
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... The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S • a Memory Management Unit (MMU) • separate instruction and data AMBA • separate instruction and data TCM interfaces 6289D–ATARM–3-Oct-11 ™ integer core ® AHB bus interfaces AT91SAM9R64/RL64 ™ family of general-purpose microproces- 49 ...
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... Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 12.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC AT91SAM9R64/RL64 50 ARM926EJ-S Coprocessor Interface Droute ...
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... User mode is the usual ARM program execution state used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 51 ...
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... R13 R14 PC CPSR The ARM state register set contains 16 directly-accessible registers r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose AT91SAM9R64/RL64 52 shows all the registers in all modes. ™ ARM9TDMI Modes and Registers Layout Supervisor ...
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... The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 53 ...
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... Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) AT91SAM9R64/RL64 Reserved Jazelle state bit ...
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... ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions 6289D–ATARM–3-Oct-11 into LR (current PC(r15 depending on the exception). (current depending on the exception) that causes the program to resume from the correct place on return. AT91SAM9R64/RL64 55 ...
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... MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP AT91SAM9R64/RL64 56 gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply ...
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... A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND AT91SAM9R64/RL64 Mnemonic Operation Move double from MRRC coprocessor Alternative move of ARM reg MCR2 to coprocessor MCRR Move double to coprocessor ...
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... Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 12-5. Register AT91SAM9R64/RL64 58 Thumb Instruction Mnemonic List (Continued) Operation Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply ...
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... Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. AT91SAM9R64/RL64 Read/Write Unpredictable/Write Read/write Read/write ...
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... L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. AT91SAM9R64/RL64 60 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 ...
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... Mapping Details Mapping Size Access Permission By 1M byte Section 64K bytes 4 separated subpages 4K bytes 4 separated subpages 1K byte Tiny Page AT91SAM9R64/RL64 ® , WindowsCE, and Linux. Subpage Size - 16K bytes 1K byte - 61 ...
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... The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. AT91SAM9R64/RL64 62 6289D–ATARM–3-Oct-11 ...
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... DCache can be enabled or disabled by writing either bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 63 ...
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... TCM region register (register 9) in CP15 maps TCMs and enables them. The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to PC-relative literal pools. AT91SAM9R64/RL64 64 6289D–ATARM–3-Oct-11 ...
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... The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 65 ...
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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. AT91SAM9R64/RL64 66 Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT that has missed in DCache) • ...
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... AT91SAM9R64/RL64 Debug and Test 13.1 Description The AT91SAM9R64/RL64 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel ...
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... Block Diagram Figure 13-1. Debug and Test Block Diagram Boundary Port ARM9EJ-S ARM926EJ-S PDC TAP: Test Access Port AT91SAM9R64/RL64 68 ICE/JTAG TAP Reset and Test ICE-RT DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR TST DTXD DRXD 6289D–ATARM–3-Oct-11 ...
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... The ICE/JTAG inter- ICE/JTAG Interface ICE/JTAG Connector RS232 AT91SAM9RL Connector AT91SAM9RLbased Application shows a test environment example. Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n Chip 2 Connector AT91SAM9RL Chip 1 AT91SAM9RL-based Application Board In Test AT91SAM9R64/RL64 Host Debugger Terminal Tester 69 ...
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... Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection Debug Unit Debug Receive Data Debug Transmit Data ™ . The scan chains are controlled by the ICE/JTAG AT91SAM9R64/RL64 Type Active Level Input Low Input/Output Low Input High Input Input ...
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... Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9R64/RL64 Debug Unit Chip ID value is 0x0196 07A0 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 13.5.5 IEEE 1149 ...
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... PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B20. • VERSION[31:28]: Product Version Number Set to 0x0. 6289D–ATARM–3-Oct- PART NUMBER MANUFACTURER IDENTITY AT91SAM9R64/RL64 26 25 PART NUMBER MANUFACTURER IDENTITY ...
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... AT91SAM9R64/RL64 Boot Program 14.1 Description The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. Then the SD Card Boot program is executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card ...
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... UTMI PLL is enabled to generate a 480MHz clock necessary to use the USB High Speed Device. 5. PLL setup: PLL is initialized to generate a 96 MHz clock. Note: 6. MCK is configured to generate a 48MHz clock (PLL/2). 7. Initialization of the DBGU serial port (115200 bauds Enable the user reset AT91SAM9R64/RL64 74 Yes Download from SD Card (MCI) Yes Download from ...
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... Internal ROM REMAP Internal SRAM 0x20 00ea000006B0x20 0x04 04eafffffeB0x04 _main 08ea00002fB_main 0x0c 0ceafffffeB0x0c 0x10 10eafffffeB0x10 0x14 14eafffffeB0x14 0x18 18eafffffeB0x18 AT91SAM9R64/RL64 0x0000_0000 Internal SRAM 0x0010_0000 Internal ROM “Structure of ARM Vector 6” on page 76). 75 ...
Page 76
... The DataFlash boot program performs device initialization followed by the download procedure. 6289D–ATARM–3-Oct- Offset (24 bits) Size of the code to download in bytes ea000006 B 0x20 eafffffe B 0x04 ea00002f B _main eafffffe B 0x0c eafffffe B 0x10 <- Code size = 4660 bytes 00001234 eafffffe B 0x18 AT91SAM9R64/RL64 ...
Page 77
... The DataFlash boot is configured to be compatible with the future design of the DataFlash. 6289D–ATARM–3-Oct-11 DataFlash Device Density 1 Mbit 2 Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits AT91SAM9R64/RL64 Table 14-1 summarizes the Page Size (bytes) Number of Pages 264 512 264 1024 264 2048 264 ...
Page 78
... SRAM and executed by branch- 6289D–ATARM–3-Oct-11 Start Send status command No Is status OK ? Yes Decode the sixth ARM vector 7 vectors No (except vector 6) are LDR or Branch instruction Yes (code size to read in vector 6) End AT91SAM9R64/RL64 Jump to next boot solution 78 ...
Page 79
... Address,# receive a file Address, NbOfBytes# go Address# display version No argument There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. AT91SAM9R64/RL64 “DataFlash Boot” on page 75 for more information Table 14-2. Example O200001,CA# o200001,# H200002,CAFE# ...
Page 80
... CRC16 Figure 14-7 6289D–ATARM–3-Oct-11 : Number of bytes in hexadecimal to receive NbOfBytes to 01) shows a transmission using this protocol. AT91SAM9R64/RL64 80 ...
Page 81
... Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature. AT91SAM9R64/RL64 Device 81 ...
Page 82
... Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. contains a list of pins that are driven during the boot program execution. These pins AT91SAM9R64/RL64 82 ...
Page 83
... Pins Driven during Boot Program Execution Pin MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 MISO MOSI SPCK NPCS0 NAND OE NAND WE NANDCS NAND ALE NAND CLE DRXD DTXD AT91SAM9R64/RL64 PIO Line PIOA0 PIOA1 PIOA2 PIOA3 PIOA4 PIOA5 PIOA25 PIOA26 PIOA27 PIOA28 PIOB4 PIOB5 PIOB6 A21 A22 PIOA21 PIOA22 ...
Page 84
... AT91SAM9R64/RL64 84 6289D–ATARM–3-Oct-11 ...
Page 85
... Block Diagram Figure 15-1. Reset Controller Block Diagram Main Supply POR Backup Supply POR NRST WDRPROC wd_fault 6289D–ATARM–3-Oct-11 Reset Controller Startup Counter Reset State Manager user_reset NRST Manager nrst_out exter_nreset SLCK AT91SAM9R64/RL64 rstc_irq proc_nreset periph_nreset backup_neset 85 ...
Page 86
... The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN RSTC_MR disables the User Reset trigger. AT91SAM9R64/RL64 86 Figure 15-2 shows the block diagram of the NRST Manager. ...
Page 87
... The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 15-3. BMS Sampling SLCK Core Supply POR output BMS Signal proc_nreset 6289D–ATARM–3-Oct-11 Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs XXX BMS sampling delay = 3 cycles AT91SAM9R64/RL64 ...
Page 88
... SLCK MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) AT91SAM9R64/RL64 88 shows how the General Reset affects the reset signals. Startup Time Processor Startup = 3 cycles XXX EXTERNAL RESET LENGTH = 2 cycles Any Freq. 0x0 = General Reset ...
Page 89
... Main Supply POR. Figure 15-5. Wake-up State SLCK MCK Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) 6289D–ATARM–3-Oct-11 Resynch. Processor Startup 2 cycles = 3 cycles XXX EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) AT91SAM9R64/RL64 Any Freq. 0x1 = WakeUp Reset XXX 89 ...
Page 90
... SLCK Any MCK Freq. NRST Resynch. 2 cycles proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) AT91SAM9R64/RL64 Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH ...
Page 91
... As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog- ress) is set in the Status Register (RSTC_SR cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 91 ...
Page 92
... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. AT91SAM9R64/RL64 92 Any Resynch. Processor Startup ...
Page 93
... The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. 6289D–ATARM–3-Oct-11 Any Freq. Processor Startup = 3 cycles Any XXX proc_nreset signal. AT91SAM9R64/RL64 0x2 = Watchdog Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 93 ...
Page 94
... URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 15-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM9R64/RL64 94 read RSTC_SR 2 cycle resynchronization 6289D–ATARM–3-Oct-11 Figure ...
Page 95
... Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read/Write Back-up Reset ...
Page 96
... No effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9R64/RL64 KEY 21 ...
Page 97
... Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low AT91SAM9R64/RL64 – – – – SRCMP NRSTL RSTTYP – ...
Page 98
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9R64/RL64 ...
Page 99
... RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV AT91SAM9R64/RL64 RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 99 ...
Page 100
... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM9R64/RL64 100 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 101
... Register Mapping Table 16-1. Real-time Timer Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 ...
Page 102
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM9R64/RL64 102 – ...
Page 103
... Returns the current value of the Real-time Timer. 6289D–ATARM–3-Oct- ALMV ALMV ALMV ALMV CRTV CRTV CRTV CRTV AT91SAM9R64/RL64 103 ...
Page 104
... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM9R64/RL64 104 – ...
Page 105
... Block Diagram Figure 17-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6289D–ATARM–3-Oct-11 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR AT91SAM9R64/RL64 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR PICNT PICNT PIT_MR PITIEN pit_irq 105 ...
Page 106
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. AT91SAM9R64/RL64 106 Figure 17-2 illustrates 6289D– ...
Page 107
... Figure 17-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6289D–ATARM–3-Oct-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR AT91SAM9R64/RL64 APB cycle APB cycle restarts MCK Prescaler 107 ...
Page 108
... Periodic Interval Timer (PIT) User Interface Table 17-1. Periodic Interval Timer (PIT) Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM9R64/RL64 108 Name Access PIT_MR Read/Write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset Value ...
Page 109
... PIV PIV – – – – – – – – – – – – AT91SAM9R64/RL64 – PITIEN PITEN PIV – – – – – – – ...
Page 110
... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. AT91SAM9R64/RL64 110 PICNT ...
Page 111
... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6289D–ATARM–3-Oct-11 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset AT91SAM9R64/RL64 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 111 ...
Page 112
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM9R64/RL64 112 6289D–ATARM–3-Oct-11 ...
Page 113
... Figure 18-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9R64/RL64 113 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6289D–ATARM–3-Oct-11 ...
Page 114
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9R64/RL64 114 Name WDT_CR WDT_MR WDT_SR KEY – ...
Page 115
... The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9R64/RL64 115 WDDBGHLT 21 ...
Page 116
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM9R64/RL64 116 – ...
Page 117
... Shutdown Controller. 6289D–ATARM–3-Oct-11 read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset SHDW_MR RTTWK SHDW_SR set read SHDW_SR reset SHDW_MR RTCWK SHDW_SR set AT91SAM9R64/RL64 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW Type Input Output 117 ...
Page 118
... SHDW_SR. When using the RTC alarm to wake up the system, the user must ensure that the RTC alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails fail. AT91SAM9R64/RL64 118 6289D–ATARM–3-Oct-11 ...
Page 119
... Shutdown Controller (SHDWC) User Interface Table 19-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0003 0x0000_0000 119 ...
Page 120
... SHDW: Shutdown Command effect KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9R64/RL64 120 KEY – – ...
Page 121
... Wake-up Input Transition Selection None. No detection is performed on the wake-up input Low to high level High to low level Both levels change AT91SAM9R64/RL64 26 25 – – – – – RTCWKEN 10 9 – – – ...
Page 122
... At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. • RTCWK: Real-time Clock Wake- wake-up alarm from the RTC occurred since the last read of SHDW_SR least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. AT91SAM9R64/RL64 122 – ...
Page 123
... Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. 6289D–ATARM–3-Oct-11 32768 Divider Time Bus Interface Entry Control AT91SAM9R64/RL64 Date Interrupt RTC Interrupt Control 123 ...
Page 124
... The following checks are performed: 1. Century (check range 19 - 20) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check BCD range 01 - 12, check validity regarding “date”) AT91SAM9R64/RL64 124 6289D–ATARM–3-Oct-11 ...
Page 125
... AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. Register Register Name RTC_CR RTC_MR RTC_TIMR RTC_CALR RTC_TIMALR RTC_CALALR RTC_SR RTC_SCCR RTC_IER RTC_IDR RTC_IMR RTC_VER (1) RTC-VERSION AT91SAM9R64/RL64 Read/Write Reset Read/Write 0x0 Read/Write 0x0 Read/Write 0x0 Read/Write 0x01819819 Read/Write 0x0 Read/Write 0x01010000 Read-only 0x0 Write-only ...
Page 126
... AT91SAM9R64/RL64 126 6289D–ATARM–3-Oct-11 ...
Page 127
... Year change (every January 1 at time 00:00:00). 6289D–ATARM–3-Oct- – – – – – – – – – – – – AT91SAM9R64/RL64 – – – – CALEVSEL – TIMEVSEL – UPDCAL UPDTIM 127 ...
Page 128
... HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected 12-hour mode is selected. All non-significant bits read zero. AT91SAM9R64/RL64 128 – – – – – – – – – ...
Page 129
... AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode AM PM. All non-significant bits read zero. 6289D–ATARM–3-Oct- – – – MIN SEC AT91SAM9R64/RL64 26 25 – – HOUR – 129 ...
Page 130
... The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Date The range that can be set (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. AT91SAM9R64/RL64 130 ...
Page 131
... This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled The hour-matching alarm is enabled. 6289D–ATARM–3-Oct- – – – MIN SEC AT91SAM9R64/RL64 26 25 – – HOUR – 131 ...
Page 132
... MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled The date-matching alarm is enabled. AT91SAM9R64/RL64 132 – ...
Page 133
... CALEV TIMEV AT91SAM9R64/RL64 – – – – – – – – – SEC ALARM ACKUPD 133 ...
Page 134
... Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear effect Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear effect Clears corresponding status flag in the Status Register (RTC_SR). AT91SAM9R64/RL64 134 – – ...
Page 135
... The selected calendar event interrupt is enabled. 6289D–ATARM–3-Oct- – – – – – – – – – – CALEN TIMEN AT91SAM9R64/RL64 – – – – – – SECEN ALREN ACKEN – – 8 – 0 135 ...
Page 136
... No effect The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable effect The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable effect The selected calendar event interrupt is disabled. AT91SAM9R64/RL64 136 – – – ...
Page 137
... The selected calendar event interrupt is enabled. 6289D–ATARM–3-Oct- – – – – – – – – – – CAL TIM AT91SAM9R64/RL64 – – – – – – – – – SEC ALR ACK 137 ...
Page 138
... No invalid data has been detected in RTC_TIMALR (Time Alarm Register RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non valid Calendar Alarm invalid data has been detected in RTC_CALALR (Calendar Alarm Register RTC_CALALR has contained invalid data since it was last programmed. AT91SAM9R64/RL64 138 – ...
Page 139
... Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus bits six chip select lines (NCS[5:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 139 ...
Page 140
... Block Diagram 21.2.1 External Bus Interface 0 Figure 21-1 Figure 21-1. Organization of the External Bus Interface 0 Bus Matrix AHB Address Decoders AT91SAM9R64/RL64 140 shows the organization of the External Bus Interface 0. External Bus Interface 0 SDRAM Controller MUX Static Logic Memory Controller CompactFlash Logic NAND Flash Logic ...
Page 141
... EBI_NWR0 - EBI_NWR3 Write Signals EBI_NBS0 - EBI_NBS3 Byte Mask Signals EBI_SDA10 SDRAM Address 10 Line 6289D–ATARM–3-Oct-11 EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller AT91SAM9R64/RL64 Type Active Level I/O Output Input Low Output Low Output Low Output ...
Page 142
... Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections (1) EBIx Pins SDRAMC I/O Lines NBS1 Not Supported Not Supported SDRAMC_A[9:0] SDRAMC_A10 Not Supported SDRAMC_A[12:11] Not Supported Not Supported D[31:0] AT91SAM9R64/RL64 SMC I/O Lines NWR1/NUB SMC_A0/NLB SMC_A1 SMC_A[11:2] Not Supported SMC_A12 SMC_A[14:13] SMC_A[22:15] SMC_A[25:23] D[31:0] 142 ...
Page 143
... NLB A0 A0 A[1:21] A[1:21] A[22:24] A[22:24 ( (1) WE NUB – – AT91SAM9R64/RL64 4 x 8-bit 2 x 16-bit 32-bit Static Static Static Devices Devices D15 D16 - D23 D24 - D31 (3) – NLB (2) (4) WE NLB A[0:20] A[0:20] A[21:23] A[21:23 ...
Page 144
... CFCS1 – – – – – OE – WE DQM1 IOR DQM3 IOW – CE1 – CE2 CLK – AT91SAM9R64/RL64 CompactFlash True IDE Mode NAND Flash (EBI only) SMC AD0-AD7 AD8-AD15 – – A0 – A1 – A[2:10] – – – – – ...
Page 145
... SDRAMC CKE – RAS – CAS – WE – – WAIT – CD1 or CD2 – – – – AT91SAM9R64/RL64 CompactFlash True IDE Mode NAND Flash (EBI only) SMC – – – – – – – – WAIT – CD1 or CD2 – ...
Page 146
... A10 A16/BA0 RAS BA0 A17/BA1 CAS BA1 DQM NBS2 128K x 8 SRAM A1-A17 D0-D7 A0-A16 D0-D7 D8-D15 CS OE NRD/NOE NRD/NOE WE A0/NWR0/NBS0 NWR1/NBS1 AT91SAM9R64/RL64 SDRAM D8-D15 D0-D7 CS CLK A0-A9, A11 A2-A11, A13 CKE SDWE A10 SDA10 WE BA0 A16/BA0 RAS BA1 A17/BA1 CAS DQM NBS1 ...
Page 147
... FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 147 ...
Page 148
... Offset 0x0000 0000 The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode). CompactFlash Mode Selection Table 21-6 AT91SAM9R64/RL64 True IDE Alternate Mode Space True IDE Mode Space I/O Mode Space Common Memory Mode Space Attribute Memory Mode Space ...
Page 149
... Access to Odd Byte on D[15:8] Don’t 1 Access to Even Byte on D[7:0] Care 1 8 bits Access to Odd Byte on D[7:0] 1 – demonstrates a schematic representation of this logic. AT91SAM9R64/RL64 SMC Access Mode Byte Select Byte Select Byte Select Byte Select Don’t Care – – Figure 149 ...
Page 150
... NWR0_NWE CFOE CFWE NRD NWR0_NWE and Table 21-9 on page 151 Table 21-9 on page 151 remain shared between all memory areas when the cor- CompactFlash Signals CS5A = 1 CFCS1 AT91SAM9R64/RL64 CompactFlash Logic 0 CFOE CFWE 1 0 CFIOR 1 CFIOW 1 1 CFIOR 1 NRD NRD illustrate the multiplexing of the Compact- ...
Page 151
... Static Memory Controller Section. 6289D–ATARM–3-Oct-11 Access to CompactFlash Device CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW illustrates an example of a CompactFlash application. CFCS0 and AT91SAM9R64/RL64 Access to Other EBI Devices EBI Signals NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25 151 ...
Page 152
... NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. See Figure Signal Multiplexing on EBI Pins” on page 153 forms, refer to the Static Memory Controller section. 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 CompactFlash Connector D[15:0] DIR /OE ...
Page 153
... EBI Note: 6289D–ATARM–3-Oct-11 NAND Flash Logic NCSx NRD D[7:0] A[22:21] NCSx/NANDCS Not Connected NANDOE NANDWE PIO PIO The External Bus Interfaces 0 and 1 are also able to support 16-bit devices. AT91SAM9R64/RL64 NANDOE NANDOE NANDWE NANDWE AD[7:0] ALE CLE NAND Flash NOE NWE CE R/B 153 ...
Page 154
... SDCK 38 SDCK CLK 1 DQML 1%6 39 CFIOR_NBS1_NWR1 DQMH CAS 17 CAS CAS RAS 18 RAS RAS SDWE 16 SDWE WE 19 SDCS_NCS1 CS 256 Mbits TSOP54 PACKAGE AT91SAM9R64/RL64 D0 2 DQ0 D1 4 DQ1 D2 5 DQ2 D3 7 DQ3 D4 8 DQ4 D5 10 DQ5 D6 11 DQ6 D7 13 DQ7 D8 42 DQ8 D9 44 ...
Page 155
... C7 100NF C7 100NF DQML VDDQ 39 DQMH 28 VSS 17 41 CAS VSS 18 54 RAS VSS 6 VSSQ 12 VSSQ VSSQ VSSQ 256 Mbits TSOP54 PACKAGE AT91SAM9R64/RL64 DQ0 MT48LC16M16A2 MT48LC16M16A2 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 ...
Page 156
... PIOs must be programmed in peripheral mode in the PIO controller. • Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. AT91SAM9R64/RL64 156 U1 U1 ...
Page 157
... R/B 10K 10K 3V3 10K 10K 1 N.C 2 N.C 3 N.C 4 N.C 5 N.C 6 N.C 10 N.C 11 N.C 14 N.C 15 N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 N.C 34 N.C 35 N.C AT91SAM9R64/RL64 MT29F2G16AABWP-ET MT29F2G16AABWP I/O9 D10 31 I/O10 D11 33 I/O11 D12 41 I/O12 D13 43 I/O13 D14 45 I/O14 D15 47 ...
Page 158
... The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. AT91SAM9R64/RL64 158 U1 U1 ...
Page 159
... RDY/BSY 11 12 3V3 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K WAIT GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 AT91SAM9R64/RL64 MEMORY & I/O MODE J1 J1 CF_D15 31 38 D15 VCC CF_D14 30 D14 CF_D13 29 13 D13 VCC CF_D12 28 D12 CF_D11 27 D11 CF_D10 49 50 ...
Page 160
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9R64/RL64 160 6289D–ATARM–3-Oct-11 ...
Page 161
... INTRQ 11 12 3V3 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K IORDY GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 AT91SAM9R64/RL64 TRUE IDE MODE J1 J1 CF_D15 31 38 D15 VCC CF_D14 30 D14 CF_D13 29 13 D13 VCC CF_D12 28 D12 CF_D11 27 D11 CF_D10 49 50 ...
Page 162
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9R64/RL64 162 6289D–ATARM–3-Oct-11 ...
Page 163
... Write or Byte Select Access” on page 165 8-/16-bit or 32-bit data bus, see “Data Bus Width” on page Byte-write or byte-select access, see Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 165 AT91SAM9R64/RL64 Type Output Output Output Output Output ...
Page 164
... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. AT91SAM9R64/RL64 164 128K x 8 SRAM ...
Page 165
... This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 6289D–ATARM–3-Oct-11 NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2. Figure 22-5 AT91SAM9R64/RL64 Figure 22-2). NCS7 Memory Enable NCS6 Memory Enable NCS5 Memory Enable ...
Page 166
... Figure 22-3. Memory Connection for an 8-bit Data Bus Figure 22-4. Memory Connection for a 16-bit Data Bus Figure 22-5. Memory Connection for a 32-bit Data Bus SMC AT91SAM9R64/RL64 166 D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD NCS[2] D[31:16] D[15:0] A[20:2] NBS0 NBS1 NBS2 NBS3 NWE NRD NCS[2] ...
Page 167
... Byte Select Access is used to connect two 16-bit devices. Figure 22-7 mode, on NCS3 (BAT = Byte Select Access). 6289D–ATARM–3-Oct-11 Figure 22-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access AT91SAM9R64/RL64 167 ...
Page 168
... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. AT91SAM9R64/RL64 168 D[7:0] D[15:8] ...
Page 169
... Bus 2x16-bit 4 x 8-bit Byte Select Byte Write NBS0 NWE NWR0 NBS1 NWR1 NBS2 NWR2 NBS3 NWR3 AT91SAM9R64/RL64 D[15:0] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable ...
Page 170
... NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. AT91SAM9R64/RL64 170 Figure 22-8. NRD_SETUP NRD_PULSE ...
Page 171
... NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 22.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Figure 22-9). 171 ...
Page 172
... NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. AT91SAM9R64/RL64 172 NRD_PULSE NRD_PULSE ...
Page 173
... Figure 22-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 6289D–ATARM–3-Oct-11 t PACC Data Sampling shows the typical read cycle of an LCD module. The read data is valid t t PACC Data Sampling AT91SAM9R64/RL64 PACC after 173 ...
Page 174
... NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 22-12. Write Cycle MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NCS_WR_SETUP AT91SAM9R64/RL64 174 NWE_SETUP NWE_PULSE NCS_WR_PULSE NWE_CYCLE Figure 22-12. The write cycle NWE_HOLD NCS_WR_HOLD 6289D–ATARM–3-Oct-11 ...
Page 175
... NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 22.8.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. 6289D–ATARM–3-Oct-11 NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE AT91SAM9R64/RL64 Figure 22-13). How- NWE_PULSE NCS_WR_PULSE NWE_CYCLE 175 ...
Page 176
... NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. AT91SAM9R64/RL64 176 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is shows the waveforms of a write operation with WRITE_MODE set to 0. The data is 6289D– ...
Page 177
... Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] AT91SAM9R64/RL64 Permitted Range Coded Value Effective Value 0 ≤ ≤ 31 128 ≤ ≤ 128+31 0 ≤ ≤ 63 256 ≤ ...
Page 178
... During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD lines are all set to 1. Figure 22-16 Select 2. AT91SAM9R64/RL64 178 gives the default value of timing parameters at reset. Reset Values of Timing Parameters Reset Value ...
Page 179
... If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See 6289D–ATARM–3-Oct-11 NRD_CYCLE Read to Write Wait State (Figure 22-17). Figure AT91SAM9R64/RL64 NWE_CYCLE Chip Select Wait State 22-19. (Figure 179 ...
Page 180
... D[31:0] Figure 22-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD D[31:0] AT91SAM9R64/RL64 180 no hold write cycle Early Read wait state no hold write cycle Early Read (READ_MODE = 0 or READ_MODE = 1) (WRITE_MODE = 0) ...
Page 181
... A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see 6289D–ATARM–3-Oct-11 MCK no hold NRD write cycle Early Read (WRITE_MODE = 1) wait state AT91SAM9R64/RL64 read setup = 1 read cycle (READ_MODE = 0 or READ_MODE = 1) “Slow Clock Mode” on page 193). 181 ...
Page 182
... SMC accesses. This wait cycle is referred read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See AT91SAM9R64/RL64 182 Figure 22-16 on page 179. 6289D–ATARM–3-Oct-11 ...
Page 183
... NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. 6289D–ATARM–3-Oct-11 ) for each external memory device is programmed in the DF will not slow down the execution of a program from internal DF illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), AT91SAM9R64/RL64 Figure 22-21 shows the read oper- 183 ...
Page 184
... NBS2, NBS3, A0, A1 NRD NCS D[31:0] Figure 22-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS D[31:0] AT91SAM9R64/RL64 184 tpacc TDF = 2 clock cycles NRD controlled read operation tpacc TDF = 3 clock cycles NCS controlled read operation 6289D–ATARM–3-Oct-11 ...
Page 185
... TDF optimization. 6289D–ATARM–3-Oct-11 shows a read access controlled by NRD, followed by a write access controlled by NRD_HOLD= 4 TDF_CYCLES = 6 Read to Write Wait State 22-23, Figure 22-24 and Figure 22-25 AT91SAM9R64/RL64 NWE_SETUP= 3 write access on NCS0 (NWE controlled) illustrate the cases: 185 ...
Page 186
... A NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 cycle TDF_CYCLES = 4 AT91SAM9R64/RL64 186 read1 hold = 1 TDF_CYCLES = 6 5 TDF WAIT STATES Chip Select Wait State read1 hold = 1 TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select Wait State ...
Page 187
... The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. 6289D–ATARM–3-Oct-11 read1 hold = 1 TDF_CYCLES = 5 read1 cycle Read to Write Wait State (“Asynchronous Page Mode” on page 193). AT91SAM9R64/RL64 write2 setup = 1 4 TDF WAIT STATES write2 cycle TDF_MODE = 0 (optimization disabled) 196 Slow Clock Mode 187 ...
Page 188
... The assertion of the NWAIT signal outside the expected period is ignored as illustrated in 22-27. Figure 22-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal AT91SAM9R64/RL64 188 FROZEN STATE Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 1 ...
Page 189
... A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6289D–ATARM–3-Oct-11 FROZEN STATE Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 AT91SAM9R64/RL64 Assertion is ignored 0 0 189 ...
Page 190
... A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal 6289D–ATARM–3-Oct- Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 AT91SAM9R64/RL64 Figure 22-28 and Figure 22-29. After Wait STATE Fig- 190 ...
Page 191
... Figure 22-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6289D–ATARM–3-Oct- Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 AT91SAM9R64/RL64 Wait STATE Assertion is ignored 191 ...
Page 192
... NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 22-30. NWAIT Latency MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWAIT intenally synchronized NWAIT signal 6289D–ATARM–3-Oct- minimal pulse length NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 AT91SAM9R64/RL64 WAIT STATE Fig- 192 ...
Page 193
... They are valid on all Table 22-6 indicates the value of read and write parameters in slow clock mode Read and Write Timing Parameters in Slow Clock Mode Duration (cycles AT91SAM9R64/RL64 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD 1 1 NCS NRD_CYCLE = 2 SLOW CLOCK MODE READ ...
Page 194
... NWE_CYCLE = 3 SLOW CLOCK MODE WRITE AT91SAM9R64/RL64 NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State ...
Page 195
... Figure 22-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK MODE WRITE 6289D–ATARM–3-Oct- IDLE STATE AT91SAM9R64/RL64 NORMAL MODE WRITE Reload Configuration Wait State 195 ...
Page 196
... A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored. shows the NRD and NCS timings in page mode access. tpa NRD_PULSE NCS_RD_PULSE AT91SAM9R64/RL64 Table 22-7. ) takes longer than the subse- pa Figure 22-34 ...
Page 197
... Access time of subsequent accesses in the page sa ‘x’ No impact ) and the NRD_PULSE for accesses to the page ( shorter than the programmed value for Figure 22- AT91SAM9R64/RL64 Table 22- Table 22-7 are identical, then the cur- illustrates access to an 8-bit memory device in ), even if sa 197 ...
Page 198
... Figure 22-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 6289D–ATARM–3-Oct-11 Page address A1 D1 NRD_PULSE NCS_RD_PULSE AT91SAM9R64/RL64 NRD_PULSE 198 ...
Page 199
... CS_number + 0x04 SMC Pulse Register 0x10 x CS_number + 0x08 SMC Cycle Register 0x10 x CS_number + 0x0C SMC Mode Register 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Table 22-9. For each chip select, a set of 4 registers is used to pro- Table 22-9, “CS_number” denotes the chip select number. Name Access ...
Page 200
... NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 6289D–ATARM–3-Oct- NCS_RD_SETUP NCS_WR_SETUP AT91SAM9R64/RL64 NRD_SETUP NWE_SETUP 200 ...