SAM9R64 Atmel Corporation, SAM9R64 Datasheet
SAM9R64
Specifications of SAM9R64
Related parts for SAM9R64
SAM9R64 Summary of contents
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... Battery Backup Power Supply, Providing a Permanent Slow Clock – 12 MHz On-chip Oscillator for Main System Clock and USB Clock – One PLL up to 240 MHz ® ® ARM Thumb Processor ® Acceleration o 2048x2048, Vir AT91 ARM Thumb Microcontrollers AT91SAM9R64 AT91SAM9RL64 Summary tual Screen 6289CS–ATARM–28-May-09 ...
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... One Four-channel 16-bit PWM Controller (PWMC) • Two Two-wire Interfaces (TWI) – Compatible with Standard Two-wire Serial Memories – One, Two or Three Bytes for Slave Address – Sequential Read/Write Operations AT91SAM9R64/RL64 2 ™ 4.3 Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding 6289CS–ATARM–28-May-09 ...
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... Some features are not available for AT91SAM9R64 in the 144-ball BGA package. Separate block diagrams and PIO multiplexing are provided in this document. features and signals of AT91SAM9RL64 that are not available or partially available for AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified. Table 1-1. Feature ...
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... Table 1-1. Feature PWM SPI SSC1 Touchscreen ADC TC TWI USART0 USART1 USART2 USART3 AT91SAM9R64/RL64 4 Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Signal Partial PWM2 NPCS2 Partial NPCS3 RF1 RK1 TD1 Full RD1 TK1 TF1 AD3YM Partial GPAD4 GPAD5 TIOA1 TIOB1 Partial ...
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... Block Diagrams Figure 2-1. AT91SAM9R64 Block Diagram 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 5 ...
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... Figure 2-2. AT91SAM9RL64 Block Diagram AT91SAM9R64/RL64 6 6289CS–ATARM–28-May-09 ...
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... Output Analog Input Output Shutdown, Wakeup Logic Output Input ICE and JTAG Input Input Output Input Input AT91SAM9R64/RL64 Comments 1.65V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 1.08V to 1.32V 3.0V to 3.6V 1. 1.32V 3.0V to 3.6V 1.08V to 1.32V Driven at 0V only. 0: The device is in backup mode. 1: The device is running (not in backup mode.) ...
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... BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset. D16-D31 not present on AT91SAM9R64 reset NCS2, NCS5 not present on AT91SAM9R64. CFCS1 not present on AT91SAM9R64. 6289CS–ATARM–28-May-09 ...
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... CTS0, CTS2, CTS3 not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. TD1 not present on AT91SAM9R64. RD1 not present on AT91SAM9R64. TK1 not present on AT91SAM9R64. RK1 not present on AT91SAM9R64. TF1 not present on AT91SAM9R64. RF1 not present on AT91SAM9R64. 9 ...
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... Not present on AT91SAM9R64. TCLK1 not present on AT91SAM9R64. TIOA1, TIOA2 not present on AT91SAM9R64. TIOB1, TIOB2 not present on AT91SAM9R64. PWM2 not present on AT91SAM9R64. NPCS2, NPCS3 not present on AT91SAM9R64. TWD1 not present on AT91SAM9R64. TWCK1 not present on AT91SAM9R64. GPAD4, GPAD5 not present on AT91SAM9R64. Multiplexed with AD0 ...
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... DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Active Type Level Comments USB High Speed Device Analog Analog Analog Analog ...
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... Package and Pinout The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available in a 217-ball LFBGA package. 4.1 144-ball BGA Package Outline Figure 4-1 Figure 4-1. 144-ball BGA Pinout (Top View) AT91SAM9R64/RL64 12 shows the orientation of the 144-ball BGA package ...
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... Pinout Table 4-1. AT91SAM9R64 Pinout for 144-ball BGA Package Pin Signal Name Pin A1 DFSDM D1 A2 DHSDM D2 A3 XIN D3 A4 XOUT D4 A5 XIN32 D5 A6 XOUT32 D6 A7 TDO D7 A8 PA[31 PA[22] D9 A10 PA[16] D10 A11 PA[14] D11 A12 PA[11] D12 B1 DFSDP E1 B2 DHSDP VDDPLLB E4 B5 GNDPLLB ...
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... LFBGA Package Outline Figure 4-2 Figure 4-2. 217-ball LFBGA Pinout (Top View) AT91SAM9R64/RL64 14 shows the orientation of the 217-ball LFBGA package BALL A1 6289CS–ATARM–28-May-09 ...
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... PB[ PB[ VDDCORE P3 H9 VDDIOP P4 H10 PD[4] P5 H14 PD[8] P6 H15 PD[5] P7 H16 PD[2] P8 H17 PD[ PB[12] P10 J2 PB[13] P11 J3 PB[11] P12 J4 PB[10] P13 J8 VDDCORE P14 J9 VDDIOP P15 J10 PC[29] P16 AT91SAM9R64/RL64 (1) Signal Name Pin PD[1] P17 PD[0] R1 PC[30] R2 PC[31] R3 PB[14] R4 PB[15] R5 PB[17] R6 PB[16] R7 VDDUTMIC R8 VDDIOP R9 PC[28] R10 PC[25] R11 PC[24] R12 PC[26] R13 PC[27] R14 PB[18] R15 PB[19] R16 PB[21] R17 PB[20] T1 PC[21] T2 PC[20] T3 PC[22] T4 ...
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... Power Considerations 5.1 Power Supplies The AT91SAM9R64/RL64 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). • ...
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... MHz with 50 pF load. 6289CS–ATARM–28-May-09 Example of PLL and USB Power Supplies VIN VOUT CE 10µF VSS MIC5235YM5 2.2µH 1V2_USB 2.2µH 1V2_USB 2.2µH 3V3 AT91SAM9R64/RL64 10µF 0.1µF 1K ADJ 100K VDDPLLB 0.1µF VDDUTMIC 0.1µF VDDUTMII 0.1µF 1V2_USB 17 ...
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... PIO Controllers All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product datasheet for more details. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “ ...
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... Matrix Masters The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 masters, which means that each master can perform an access concurrently with others available slave. Each master has its own decoder, which is defined specifically for each master. In order to sim- plify the addressing, all the masters have the same decodings. ...
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... Table 7-1. Master 3 Master 4 Master 5 7.3 Matrix Slaves The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 7.4 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “ ...
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... Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 6289CS–ATARM–28-May-09 USART0 Transmit Channel SSC1 Transmit Channel SSC0 Transmit Channel DBGU Receive Channel AC97 Receive Channel SSC1 Receive Channel AT91SAM9R64/RL64 21 ...
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... Memories Figure 8-1. AT91SAM9R64/RL64 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes Chip Select 2 ...
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... Notes: 8.1.1.1 Internal SRAM The AT91SAM9R64/RL64 product embeds a total of 64Kbyte high-speed SRAM split in 4 blocks of 16KBytes. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. ...
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... RB2 SRAM C 0x0030 8000 RB1 (AHB) 0x0030 C000 RB0 Note: 1. Configuration after reset. AT91SAM9R64/RL64 24 0 16K Bytes 32K Bytes illustrates different configurations and the related 16-Kbyte blocks (RB0 to RB3) Configuration examples and related 16-Kbyte block assignments I = 16K I =32K ...
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... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The AT91SAM9R64/RL64 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect ...
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... Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock • Switch the main clock to the new value 8.2 External Memories The AT91SAM9R64/RL64 features one External Bus Interface to offer interface to a wide range of external memories and to any parallel peripheral. 8.2.1 External Bus Interface • Integrates three External Memory Controllers: – ...
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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 6289CS–ATARM–28-May-09 detected erroneous pages AT91SAM9R64/RL64 27 ...
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... However, all the registers of System Controller are mapped on the top of the address space. This allows addressing all the registers of the System Controller from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of +/- 4kbytes. AT91SAM9R64/RL64 28 Figure 8-1, the System Controller’s peripherals are all mapped within the highest ...
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... MAINCK PCK Power Management MCK Controller HSCK pmc_irq idle PLLACK periph_irq[2..4] irq dbgu_rxd PIO fiq Controllers dbgu_txd AT91SAM9R64/RL64 nirq nfiq ntrst ARM926EJ-S por_ntrst proc_nreset PCK debug jtag_nreset Boundary Scan TAP Controller MCK Bus Matrix periph_nreset HSCK periph_clk[22] USB High Speed ...
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... One 80 to 240 MHz programmable PLL, providing the PLL Clock (PLLCK). This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 1 MHz. AT91SAM9R64/RL64 30 6289CS–ATARM–28-May-09 ...
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... Slow Clock Selection 9.6.1 Description The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external slow clock on XIN32. Configuration is located in the slow clock control register (SCKCR) located at address 0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is present. Refer to the “ ...
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... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9R64/RL64 Power Management Controller Block Diagram Master Clock Controller SLCK MAINCK PLLCK 9 ...
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... Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes 6289CS–ATARM–28-May-09 enabled processor Generator AT91SAM9R64/RL64 33 ...
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... Peripheral Mapping As shown in space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. AT91SAM9R64/RL64 34 the ARM Processor’s ICE Interface Figure 8-1, the Peripherals are mapped in the upper 256M bytes of the address 6289CS–ATARM–28-May-09 ...
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... DMAC 22 UDPHS 23 LCDC 24 AC97 25- AIC Note: 6289CS–ATARM–28-May-09 defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral iden- Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D USART 0 USART 1 USART 2 USART 3 Multimedia Card Interface ...
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... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.4 Peripherals Signals Multiplexing on I/O Lines The AT91SAM9R64/RL64 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which mul- tiplexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... RF1 I/O VDDIOP RK1 I/O VDDIOP RK0 I/O VDDIOP I/O VDDIOP I/O VDDIOP TD1 I/O VDDIOP RD1 I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDANA RTS1 I/O VDDANA CTS1 I/O VDDANA SCK3 I/O VDDANA I/O VDDIOP RF0 I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP TF1 I/O VDDIOP TK1 I/O VDDIOP IRQ I/O VDDIOP AT91SAM9R64/RL64 Application Usage Function Comments 37 ...
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... PB20 D20 PB21 D21 PB22 D22 PB23 D23 PB24 D24 PB25 D25 PB26 D26 PB27 D27 PB28 D28 PB29 D29 PB30 D30 PB31 D31 AT91SAM9R64/RL64 38 Reset Power Peripheral B State Supply I/O VDDIOP I/O VDDIOP A21 VDDIOM A22 VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM NPCS1 I/O VDDIOM ...
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... VDDIOP LCDD7 I/O VDDIOP LCDD10 I/O VDDIOP LCDD11 I/O VDDIOP LCDD12 I/O VDDIOP LCDD13 I/O VDDIOP LCDD14 I/O VDDIOP LCDD15 I/O VDDIOP LCDD18 I/O VDDIOP LCDD19 I/O VDDIOP LCDD20 I/O VDDIOP LCDD21 I/O VDDIOP LCDD22 I/O VDDIOP LCDD23 I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP TIOA1 I/O VDDIOP TIOB1 I/O VDDIOP TCLK1 I/O VDDIOP AT91SAM9R64/RL64 Application Usage Function Comments 39 ...
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... TIOB2 PD12 PWM2 PCK1 PD13 NCS5/CFCS1 NPCS3 PD14 DSR0 PWM0 PD15 DTR0 PWM1 PD16 DCD0 PWM2 PD17 RI0 PD18 PWM3 PD19 PCK0 PD20 PCK1 PD21 TCLK2 AT91SAM9R64/RL64 40 Reset Power Comments State Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDANA I/O VDDANA I/O VDDIOP I/O ...
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... AT91SAM9R64 PIO Multiplexing Note: In Table 10-6, Table 10-7, Table 10-8 AT91SAM9R64. 10.4.2.1 AT91SAM9R64 PIO Controller A Multiplexing Table 10-6. AT91SAM9R64 Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 MC_DA0 PA1 MC_CDA PA2 MC_CK PA3 MC_DA1 PA4 MC_DA2 PA5 MC_DA3 PA6 TXD0 PA7 RXD0 PA8 NA PA9 NA PA10 CTS0 ...
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... AT91SAM9R64 PIO Controller B Multiplexing Table 10-7. AT91SAM9R64 Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 TXD3 PB1 RXD3 PB2 A21/NANDALE PB3 A22/NANDCLE PB4 NANDOE PB5 NANDWE PB6 NCS3/NANDCS PB7 NCS4/CFCS0 PB8 CFCE1 PB9 CFCE2 PB10 A25/CFRNW PB11 A18 PB12 A19 PB13 A20 ...
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... AT91SAM9R64 PIO Controller C Multiplexing Table 10-8. AT91SAM9R64 Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 TF0 PC1 TK0 PC2- NA PC31 10.4.2.4 AT91SAM9R64 PIO Controller D Multiplexing Table 10-9. AT91SAM9R64 Multiplexing on PIO Controller D PIO Controller D I/O Line Peripheral A Peripheral B PD0- NA PD17 PD18 PWM3 PD19 PCK0 PD20 PCK1 ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first AT91SAM9R64/RL64 44 peripherals Sensors and data per chip select ...
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... Variable sampling rate AC97 Codec Interface (48KHz and below) 11.6 Timer Counter (TC) • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 2 S, TDM Buses, Magnetic Card Reader, etc.) 45 ...
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... USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver • Embedded 4K-byte dual-port RAM for endpoints • Embedded 6 channels DMA controller • Suspend/Resume logic • banks for isochronous and bulk endpoints • Seven endpoints: AT91SAM9R64/RL64 46 6289CS–ATARM–28-May-09 ...
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... Multiple trigger sources – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all 6289CS–ATARM–28-May-09 enabled channels AT91SAM9R64/RL64 47 ...
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... Package Drawings Figure 12-1. 144-ball BGA Package Drawing AT91SAM9R64/RL64 48 6289CS–ATARM–28-May-09 ...
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... Figure 12-2. 217-ball LFBGA Package Drawing 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 49 ...
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... AT91SAM9R64/RL64 Ordering Information Table 13-1. AT91SAM9R64/RL64 Ordering Information Ordering Code MRL AT91SAM9R64-CU AT91SAM9RL64-CU AT91SAM9R64/RL64 50 Package A LFBGA144 A LFBGA217 Package Type Temperature Operating Range Green Industrial -40°C to 85°C Green 6289CS–ATARM–28-May-09 ...
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... Pins”, removed information on the shutdown pin ROM”, – SDCard, (boot ROM does not support high 2, updated Mapping”, Internal Memory Mapping updated. Slaves”, Table 7-3, “AT91SAM9R64/RL64 Master to Slave and Figure 5-1 List”, additional comments on BMS. PB8, PB9 Peripheral A column: typos corrected, “CFCE1”, “CFCE2”. ...
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