SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 6

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Contents
vi
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Memory Interface
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Coprocessor Interface
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Debug Interface
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Instruction Cycle Timings
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
About the memory interface ....................................................................... 3-2
Bus interface signals .................................................................................. 3-3
Bus cycle types ........................................................................................... 3-4
Addressing signals ................................................................................... 3-11
Address timing .......................................................................................... 3-14
Data timed signals .................................................................................... 3-17
Stretching access times ............................................................................ 3-29
Action of ARM7TDMI core in debug state ................................................ 3-31
Privileged mode access ............................................................................ 3-32
Reset sequence after power up ................................................................ 3-33
About coprocessors .................................................................................... 4-2
Coprocessor interface signals .................................................................... 4-4
Pipeline following signals ............................................................................ 4-5
Coprocessor interface handshaking ........................................................... 4-6
Connecting coprocessors ......................................................................... 4-12
If you are not using an external coprocessor ............................................ 4-15
Undefined instructions .............................................................................. 4-16
Privileged instructions ............................................................................... 4-17
About the debug interface .......................................................................... 5-2
Debug systems ........................................................................................... 5-4
Debug interface signals .............................................................................. 5-6
ARM7TDMI core clock domains ............................................................... 5-10
Determining the core and system state .................................................... 5-12
About EmbeddedICE Logic ...................................................................... 5-13
Disabling EmbeddedICE .......................................................................... 5-15
Debug Communications Channel ............................................................. 5-16
About the instruction cycle timing tables .................................................... 6-3
Branch and branch with link ....................................................................... 6-4
Thumb branch with link ............................................................................... 6-5
Branch and Exchange ................................................................................ 6-6
Data operations .......................................................................................... 6-7
Multiply and multiply accumulate ................................................................ 6-9
Load register ............................................................................................. 6-12
Store register ............................................................................................ 6-14
Load multiple registers ............................................................................. 6-15
Store multiple registers ............................................................................. 6-17
Data swap ................................................................................................. 6-18
Software interrupt and exception entry ..................................................... 6-19
Coprocessor data operation ..................................................................... 6-20
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