SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 896
SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
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- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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40.5.2.2
40.5.2.3
896
896
SAM9G35
SAM9G35
Start Detection and Data Sampling
Receiver Ready
The programmer can also put the receiver in its reset state by writing UART_CR with the bit
RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled,
whatever its current state. If RSTRX is applied when data is being processed, this data is lost.
The UART only supports asynchronous operations, and this affects only its receiver. The UART
receiver detects the start of a received character by sampling the URXD signal until it detects a
valid start bit. A low level (space) on URXD is interpreted as a valid start bit if it is detected for
more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is
longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit
period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the URXD at the theoretical mid-
point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period)
so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling
point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 40-3. Start Bit Detection
Figure 40-4. Character Reception
When a complete character is received, it is transferred to the UART_RHR and the RXRDY sta-
tus bit in UART_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register UART_RHR is read.
Example: 8-bit, parity enabled 1 stop
Sampling Clock
Sampling
URXD
Baud Rate
URXD
Clock
0.5 bit
period
True Start Detection
period
1 bit
D0
D1
True Start
Detection
D2
D3
D4
D5
D6
D7
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Parity Bit
Stop Bit
D0
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