SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 1251

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.17.4.2
Table 46-41. EMAC Signals Relative to EMDC
Notes:
Figure 46-21. Min and Max access time of EMAC output signals
46.17.4.3
Table 46-42. EMAC RMII Timings
Notes:
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Symbol
EMAC
EMAC
EMAC
Symbol
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
1
2
3
21
22
23
24
25
26
27
28
1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC rising
1. See Note
edge and the signal change. The Max access timing is the time between the EDMC rising edge and the signal stabilizes.
Figure 46-21
Timing constraints
RMII Mode
EMDC
EMDIO
(4)
Parameter
Setup for EMDIO from EMDC rising
Hold for EMDIO from EMDC rising
EMDIO toggling from EMDC rising
Parameter
ETXEN toggling from EREFCK rising
ETX toggling from EREFCK rising
Setup for ERX from EREFCK rising
Hold for ERX from EREFCK rising
Setup for ERXER from EREFCK rising
Hold for ERXER from EREFCK rising
Setup for ECRSDV from EREFCK rising
Hold for ECRSDV from EREFCK rising
of
illustrates Min and Max accesses for EMAC3.
Table
46-41.
EMAC
4
EMAC
EMAC
1
5
EMAC
2
Min (ns)
Min (ns)
0 ns
EMAC
10 ns
10 ns
2
2
EMAC
4
2
2
4
2
4
(1)
(1)
(1)
3 min
3 max
SAM9G35
SAM9G35
Max (ns)
Max (ns)
300 ns
16
16
(1)
(1)
(1)
1251
1251