SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 1061

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45. LCD Controller (LCDC)
45.1
45.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Description
Embedded Characteristics
The LCD controller consists of logic for transferring LCD image data from an external display
buffer to an LCD module. The LCD has one display input buffer per overlay that fetches pixels
through the AHB master interface and a lookup table to allow palletized display configurations.
The LCD controller is programmable on a per overlay basis, and supports different LCD resolu-
tion, window size, image format and pixel depth.
The LCD is connected to the ARM Advanced High Performance Bus (AHB) as a master for
reading pixel data. It also integrates an APB interface to configure its registers.
• One AHB Master Interface
• Supports Single Scan Active TFT Display
• Supports 12-, 16-, 18- and 24-bit Output Mode through the Spatial Dithering Unit
• Asynchronous Output Mode Supported
• 1, 2, 4, 8 bits per pixel (palletized)
• 12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized)
• Supports One Base Layer (background)
• Supports Ovr1 Layer Window
• Supports One High End Overlay (HEO) Window
• Supports One Hardware Cursor, Free Ranging up to a size limit of 128x128 pixels
• Little Endian Memory Organization
• Programmable Timing Engine, with Integer Clock Divider
• Programmable Polarity for Data, Line Synchro and Frame Synchro
• Hardware Cursor Fixed Size on the following patterns: 32x32, 64x64 and 128x128
• Display Size up to 800 x 600
• Color Lookup Table with up to 256 entries and Predefined 8-bit Alpha
• Programmable Negative and Positive Row Striding for all layers
• Programmable Negative and Positive Pixel Striding for all Overlay1 and HEO layers
• High End Overlay supports 4:2:0 Planar Mode and Semiplanar Mode
• High End Overlay supports 4:2:2 Planar Mode and Packed Memory Mode
• High End Overlay includes Chroma Upsampling unit and Programmable Scaler
• Integrates Fully Programmable Color Space Conversion
• Overlay1 and High End Overlay integrate Rotation Engine: 90, 180, 270
• Blender Function Supports Arbitrary 8-bit Alpha value and Chroma Keying
• DMA User interface uses Linked List Structure and Add-to-queue Structure
SAM9G35
SAM9G35
1061
1061