SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 147
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SAM7XC512
Manufacturer Part Number
SAM7XC512
Description
Manufacturer
Atmel Corporation
Specifications of SAM7XC512
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
128
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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6.3
ARM DDI 0029G
Thumb branch with link
A Thumb Branch with Link operation consists of two consecutive Thumb instructions.
Refer to the ARM Architecture Reference Manual for more information.
The first instruction acts like a simple data operation to add the PC to the upper part of
the offset, storing the result in Register 14, LR.
The second instruction which takes a single cycle acts in a similar fashion to the ARM
state branch with link instruction. The first cycle therefore calculates the final branch
destination whilst performing a prefetch from the current PC.
The second cycle of the second instruction performs a fetch from the branch destination
and the return address is stored in R14.
The third cycle of the second instruction performs a fetch from the destination +2,
refilling the instruction pipeline and R14 is modified, with 2 subtracted from it, to
simplify the return to
subroutine work correctly.
The cycle timings of the complete operation are listed in Table 6-2 where:
•
pc is the address of the first instruction of the operation.
Cycle
1
2
3
4
Copyright © 1994-2001. All rights reserved.
Address
pc+4
pc+6
alu
alu+2
alu+4
MAS[1:0]
1
1
1
1
. This makes the
nRW
0
0
0
0
Table 6-2 Thumb long branch with link
Data
(pc+4)
(pc+6)
(alu)
(alu+2)
nMREQ
0
0
0
0
Instruction Cycle Timings
SEQ
1
0
1
1
nOPC
0
0
0
0
type of
6-5
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