SAM7XC512 Atmel Corporation, SAM7XC512 Datasheet - Page 145

• Manufacturer Part Number: SAM7XC512
• Manufacturer: Atmel Corporation

Specifications of SAM7XC512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6.1
ARM DDI 0029G
About the instruction cycle timing tables
In the following tables:
•
•
•
•
•
•
nMREQ and SEQ, are pipelined up to one cycle ahead of the cycle to which they
apply. They are shown in the cycle in which they appear and indicate the next
cycle type.
The address, MAS[1:0], nRW, nOPC, nTRANS, and TBIT signals, that appear
up to half a cycle ahead, are shown in the cycle to which they apply. The address
is incremented to prefetch instructions in most cases. Because the instruction
width is four bytes in ARM state and two bytes in Thumb state, the increment
varies accordingly.
The letter L is used to indicate instruction length:
—
—
The letter i is used to indicate the width of the instruction fetch output by
MAS[1:0]:
—
—
Terms placed inside brackets represent the contents of an address.
The • symbol indicates zero or more cycles.
Copyright © 1994-2001. All rights reserved.
four bytes in ARM state
two bytes in Thumb state.
i=2 in ARM state represents word accesses
i=1 in Thumb state represents halfword accesses.
Instruction Cycle Timings
6-3