SAM7XC256 Atmel Corporation, SAM7XC256 Datasheet - Page 61
SAM7XC256
Manufacturer Part Number
SAM7XC256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7XC256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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2.7.3
ARM DDI 0029G
M[4:0]
10000
10001
10010
10011
10111
11011
11111
Reserved bits
Mode
User
FIQ
IRQ
Supervisor
Abort
Undefined
System
Mode bits
Bits M[4:0] determine the processor operating mode as shown in Table 2-2. Not all
combinations of the mode bits define a valid processor mode, so take care to use only
the bit combinations shown.
An illegal value programmed into M[4:0] causes the processor to enter an
unrecoverable state. If this occurs, apply reset.
The remaining bits in the PSRs are unused, but are reserved. When changing a PSR flag
or control bits, make sure that these reserved bits are not altered. Also, make sure that
your program does not rely on reserved bits containing specific values because future
processors might have these bits set to 1 or 0.
Visible Thumb-state registers
r0–r7, SP, LR, PC, CPSR
r0–r7, SP_fiq, LR_fiq, PC, CPSR, SPSR_fiq
r0–r7, SP_irq, LR_irq, PC, CPSR, SPSR_irq
r0–r7, SP_svc, LR_svc, PC, CPSR,
SPSR_svc
r0–r7, SP_abt, LR_abt, PC, CPSR,
SPSR_abt
r0–r7, SP_und, LR_und, PC, CPSR,
SPSR_und
r0–r7, SP, LR, PC, CPSR
Copyright © 1994-2001. All rights reserved.
Visible ARM-state registers
r0–r14, PC, CPSR
r0–r7, r8_fiq–r14_fiq, PC, CPSR,
SPSR_fiq
r0–r12, r13_irq, r14_irq, PC, CPSR,
SPSR_irq
r0–r12, r13_svc, r14_svc, PC, CPSR,
SPSR_svc
r0–r12, r13_abt, r14_abt, PC, CPSR,
SPSR_abt
r0–r12, r13_und, r14_und, PC, CPSR,
SPSR_und
r0–r14, PC, CPSR
Table 2-2 PSR mode bit values
Programmer’s Model
2-15
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