SAM7XC256 Atmel Corporation, SAM7XC256 Datasheet - Page 60
SAM7XC256
Manufacturer Part Number
SAM7XC256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7XC256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Programmer’s Model
2.7.2
2-14
Control bits
All instructions can execute conditionally in ARM state. In Thumb state, only the
Branch instruction can be executed conditionally. For more information about
conditional execution, refer to the ARM Architecture Reference Manual.
The bottom eight bits of a PSR are known collectively as the control bits. They are the:
•
•
•
The control bits change when an exception occurs. When the processor is operating in
a privileged mode, software can manipulate these bits.
Interrupt disable bits
The I and F bits are the interrupt disable bits:
•
•
T bit
The T bit reflects the operating state:
•
•
The operating state is reflected on the external signal TBIT.
Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If
you do this, the processor enters an unpredictable state.
interrupt disable bits
T bit
mode bits.
when the I bit is set, IRQ interrupts are disabled
when the F bit is set, FIQ interrupts are disabled.
when the T bit is set, the processor is executing in Thumb state
when the T bit is clear, the processor executing in ARM state.
Caution
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G
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