SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 214

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• TWR: Write Recovery Delay
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 2 and 15.
If TWR is less than or equal to 2, two clock periods are inserted by default.
• TRC: Row Cycle Delay
Reset value is eight cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is
between 2 and 15.
If TRC is less than or equal to 2, two clock periods are inserted by default.
• TRP: Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles
is between 2 and 15.
If TRP is less than or equal to 2, two clock periods are inserted by default.
• TRCD: Row to Column Delay
Reset value is three cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 2 and 15.
If TRCD is less than or equal to 2, two clock periods are inserted by default.
• TRAS: Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 2 and 15.
If TRAS is less than or equal to 2, two clock periods are inserted by default.
• TXSR: Exit Self Refresh to Active Delay
Reset value is five cycles.
This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is
between 1/2 and 15.5.
If TXSR is equal to 0, 1/2 clock period is inserted by default.
214
0
0
1
1
CAS
SAM7SE512/256/32
0
1
0
1
CAS Latency (Cycles)
Reserved
Reserved
Reserved
2
6222F–ATARM–14-Jan-11