SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 196

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.7.1
Name:
Access:
Reset Value:
• NWS: Number of Wait States
This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles.
Note:
Note:
• WSEN: Wait State Enable
0: Wait states are disabled.
1: Wait states are enabled.
• TDF: Data Float Time
The external bus is marked occupied and cannot be used by another chip select during TDF cycles. Up to 15 cycles can be
defined and represents the time allowed for the data output to go to high impedance after the memory is disabled.
• BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
0: Chip select line is connected to two 8-bit wide devices.
1: Chip select line is connected to a 16-bit wide device.
196
Number of Wait States
WSEN
DRP
31
23
15
–
–
7
When WSEN is 0, NWS will be read to 0 whichever the previous programmed value should be.
1. Assuming WSEN Field = 0.
X + 1
SAM7SE512/256/32
SMC Chip Select Registers
0
1
2
(1)
30
22
14
SMC_CSR0..SMC_CSR7
Read/Write
See
–
6
Table 22-4 on page 195
DBW
Up to X = 127
NWS Field
Don’t Care
RWHOLD
0
1
29
21
13
–
5
Standard Read Protocol
BAT
NRD Pulse Length
28
20
12
–
4
X + 1+ ½ cycles
1 + ½ cycles
2 + ½ cycles
½ cycle
NWS
27
19
11
–
–
3
Early Read Protocol
NRD Pulse Length
X + 2 cycles
2 cycles
3 cycles
1 cycle
26
18
10
–
2
TDF
RWSETUP
25
17
9
1
NWR Pulse Length
6222F–ATARM–14-Jan-11
ACSS
X + 1 cycle
2 cycles
½ cycle
1 cycle
24
16
8
0