SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 202

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

23.5
23.5.1
202
Product Dependencies
SAM7SE512/256/32
SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
After initialization, the SDRAM devices are fully functional.
Note:
1. SDRAM Characteristics must be set in the Configuration Register: asynchronous tim-
2. A minimum pause of 200 µs is provided to precede any signal toggle.
3.
4. An All Banks Precharge command is issued to the SDRAM devices. The application
5. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in
6. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM
7. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and
8. Write the refresh rate into the count field in the SDRAMC Refresh Timer Register.
ings (TRC, TRAS,...), number of columns, rows, and CAS latency. The data bus width
must be set in the Mode Register.
(1)
1 in the Mode Register and perform a write access to any SDRAM address.
must set Mode to 2 in the Mode Register and perform a write access to any SDRAM
address.
the Mode Register and performs a write access to any SDRAM location height times.
devices, in particular CAS latency and burst length. The application must set Mode to 3
in the Mode Register and perform a write access to the SDRAM.
performing a write access at any location in the SDRAM.
(Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh
every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the Refresh Timer Counter
Register must be set with the value 1562(15.652 µs x 100 MHz) or 781(7.81 µs x 100
MHz).
A NOP command is issued to the SDRAM devices. The application must set Mode to
1. It is strongly recommended to respect the instructions stated in step
cess in order to be certain that the following commands issued by the SDRAMC will be well
taken into account.
3
of the initialization pro-
6222F–ATARM–14-Jan-11