SAM7S32 Atmel Corporation, SAM7S32 Datasheet - Page 537
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SAM7S32
Manufacturer Part Number
SAM7S32
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S32
Flash (kbytes)
32 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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36.5
36.5.1
36.5.2
36.5.3
6175L–ATARM–28-Jul-11
Functional Description
Analog-to-digital Conversion
Conversion Reference
Conversion Resolution
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-
bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the
Mode Register” on page 544
the PRESCAL field of the Mode Register (ADC_MR).
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to
63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency accord-
ing to the parameters given in the Product definition section.
The conversion is performed on a full range between 0V and the reference voltage pin ADVREF.
Analog inputs between these voltages convert to values based on a linear conversion.
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit
LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the
highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the
ADC switches in the lowest resolution and the conversion results can be read in the eight lowest
significant bits of the data registers. The two highest bits of the DATA field in the corresponding
ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer
request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In
this case, the destination buffers are optimized.
and 10 ADC Clock cycles. The ADC Clock frequency is selected in
SAM7S Series
“ADC
537
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